摘要:
Methods and apparatus for package on package structures having stud bump through via interconnections. A structure includes an interconnect layer having a plurality of through via assemblies each including at least one stud bump are formed on conductive pads; and encapsulant surrounding the through via assembly, a first redistribution layer formed over a surface of the encapsulant and coupled to the through via assemblies and carrying connectors, and a second redistribution layer over interconnect layer at the other end of the through via assemblies, the through via assemblies extending vertically through the interconnect layer. In an embodiment the interconnect layer is mounted using the connectors to a lower package substrate to form a package on package structure. A first integrated circuit device may be mounted on the second redistribution layer of the interconnect layer. Methods for forming the interconnect layer and the package on package structures are disclosed.
摘要:
A device includes a Through-Assembly Via (TAV) Module, which includes a substrate, a plurality of through-vias penetrating through the substrate, and a second plurality of metal posts at a bottom surface of the TAV module and electrically coupled to the plurality of through-vias. A polymer includes a first portion between and contacting sidewalls of the first package component and the TAV module, a second portion disposed between the first plurality of metal posts, and a third portion disposed between the second plurality of metal posts. A first plurality of Redistribution Lines (RDLs) is underlying a bottom surface of the second and the third portions of the polymer. A second plurality of RDLs is over the first package component and the TAV module. The first plurality of RDLs is electrically coupled to the second plurality of RDLs through the plurality of through-vias in the TAV module.
摘要:
A discrete Through-Assembly Via (TAV) module includes a substrate, and vias extending from a surface of the substrate into the substrate. The TAV module is free from conductive features in contact with one end of each of the conductive vias.
摘要:
A T-shaped post for semiconductor devices is provided. The T-shaped post has an under-bump metallization (UBM) section and a pillar section extending from the UBM section. The UBM section and the pillar section may be formed of a same material or different materials. In an embodiment, a substrate, such as a die, wafer, printed circuit board, packaging substrate, or the like, having T-shaped posts is attached to a contact of another substrate, such as a die, wafer, printed circuit board, packaging substrate, or the like. The T-shaped posts may have a solder material pre-formed on the pillar section such that the pillar section is exposed or such that the pillar section is covered by the solder material. In another embodiment, the T-shaped posts may be formed on one substrate and the solder material formed on the other substrate.
摘要:
An integrated circuit structure includes a first work piece and a second work piece. The first work piece includes a copper bump at a main surface of the first work piece and having a first dimension; and a nickel-containing barrier layer over and adjoining the copper bump. The second work piece is bonded to the first work piece and includes a bond pad at a main surface of the second work piece; and a solder mask at the main surface of the second work piece and having a solder resist opening with a second dimension exposing a portion of the bond pad. A ratio of the first dimension to the second dimension is greater than about 1. Further, a solder region electrically connects the copper bump to the bond pad, with a vertical distance between the bond pad and the copper bump being greater than about 30 μm.
摘要:
An integrated circuit structure includes a first work piece and a second work piece. The first work piece includes a copper bump at a main surface of the first work piece and having a first dimension; and a nickel-containing barrier layer over and adjoining the copper bump. The second work piece is bonded to the first work piece and includes a bond pad at a main surface of the second work piece; and a solder mask at the main surface of the second work piece and having a solder resist opening with a second dimension exposing a portion of the bond pad. A ratio of the first dimension to the second dimension is greater than about 1. Further, a solder region electrically connects the copper bump to the bond pad, with a vertical distance between the bond pad and the copper bump being greater than about 30 μm.
摘要:
A T-shaped post for semiconductor devices is provided. The T-shaped post has an under-bump metallization (UBM) section and a pillar section extending from the UBM section. The UBM section and the pillar section may be formed of a same material or different materials. In an embodiment, a substrate, such as a die, wafer, printed circuit board, packaging substrate, or the like, having T-shaped posts is attached to a contact of another substrate, such as a die, wafer, printed circuit board, packaging substrate, or the like. The T-shaped posts may have a solder material pre-formed on the pillar section such that the pillar section is exposed or such that the pillar section is covered by the solder material. In another embodiment, the T-shaped posts may be formed on one substrate and the solder material formed on the other substrate.
摘要:
Methods for forming lead free solder interconnections for integrated circuits. A copper column extends from an input/output terminal of an integrated circuit. A cap layer of material is formed on the input/output terminal of the integrated circuit. A lead free solder connector is formed on the cap layer. A substrate having a metal finish solder pad is aligned with the solder connector. An intermetallic compound is formed at the interface between the cap layer and the lead free solder connector. A solder connection is formed between input/output terminal of the integrated circuit and the metal finish pad that is less than 0.5 weight percent copper, and the intermetallic compound is substantially free of copper.
摘要:
Lead free solder interconnections for integrated circuits. A copper column extends from an input/output terminal of an integrated circuit. A cap layer of material is formed on the input/output terminal of the integrated circuit. A lead free solder connector is formed on the cap layer. A substrate having a metal finish solder pad is aligned with the solder connector. An intermetallic compound is formed at the interface between the cap layer and the lead free solder connector. A solder connection is formed between the input/output terminal of the integrated circuit and the metal finish pad that is less than 0.5 weight percent copper, and the intermetallic compound is substantially free of copper.
摘要:
Apparatus and methods for providing a robust solder connection in a flip chip arrangement using lead free solder are disclosed. A copper column extends from an input/output terminal of an integrated circuit. A cap layer of a material comprising one of nickel, nickel alloys, palladium, platinum, cobalt, silver, gold, and alloys of these is formed on the exterior surface of the copper column. A lead free solder connector is disposed on the cap layer. A substrate having a metal finish solder pad is aligned with the solder connector. A thermal reflow is performed. The metal finish may be of nickel, nickel alloy and nickel based materials. Following a thermal reflow, the solder connection formed between the copper terminal column and the metal finish solder pad is less than 0.5 wt. %.