公开(公告)号：US20140264785A1

公开(公告)日：2014-09-18

申请号：US14207224

申请日：2014-03-12

Applicant: XINTEC INC.

Inventor： Yi-Min LIN ,  Yi-Ming CHANG ,  Shu-Ming CHANG ,  Yen-Shih HO ,  Tsang-Yu LIU ,  Chia-Ming CHENG

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/78

CPC classification number: H01L23/552 ,  H01L21/4814 ,  H01L21/78 ,  H01L23/544 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2223/5446 ,  H01L2224/02313 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/0239 ,  H01L2224/03614 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/451 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/4847 ,  H01L2224/92 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01078 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2924/014 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed over the first surface and extending into the first recess and/or the second recess; an insulating layer positioned between the wire layer and the semiconductor substrate; and a metal light shielding layer disposed over the first surface and having at least one hole, wherein a shape of the at least one hole is a quadrangle.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有第一表面和第二表面的半导体衬底; 从所述第一表面延伸到所述第二表面的第一凹部; 从所述第一凹部的底部朝向所述第二表面延伸的第二凹部，其中所述第一凹部的侧壁和所述底部以及所述第二凹部的第二侧壁和第二底部一起形成所述半导体衬底的外侧表面; 布置在所述第一表面上并延伸到所述第一凹部和/或所述第二凹部中的导线层; 位于所述导线层和所述半导体基板之间的绝缘层; 以及设置在所述第一表面上并且具有至少一个孔的金属遮光层，其中所述至少一个孔的形状是四边形。

公开(公告)号：US20130307161A1

公开(公告)日：2013-11-21

申请号：US13895219

申请日：2013-05-15

Applicant: Xintec Inc.

Inventor： Shu-Ming CHANG ,  Yu-Ting HUANG ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L23/538 ,  H01L21/78

CPC classification number: H01L23/5384 ,  B81B7/007 ,  B81B2207/095 ,  B81B2207/096 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/481 ,  H01L23/60 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05617 ,  H01L2224/05624 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2924/10155 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2224/80 ,  H01L2224/83 ,  H01L21/304 ,  H01L21/76898 ,  H01L2221/68304 ,  H01L2224/0231 ,  H01L2224/11

Abstract: An embodiment of the invention provides a chip package which includes: a first substrate; a second substrate disposed thereon, wherein the second substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer therebetween, and a portion of the lower semiconductor layer electrically contacts with at least one pad on the first substrate; a conducting layer disposed on the upper semiconductor layer of the second substrate and electrically connected to the portion of the lower semiconductor layer electrically contacting with the at least one pad; an opening extending from the upper semiconductor layer towards the lower semiconductor layer and extending into the lower semiconductor layer; and a protection layer disposed on the upper semiconductor layer and the conducting layer, wherein the protection layer extends onto a portion of a sidewall of the opening, and does not cover the lower semiconductor layer in the opening.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：第一基板; 设置在其上的第二基板，其中所述第二基板包括下半导体层，上半导体层和绝缘层，并且所述下半导体层的一部分与所述第一基板上的至少一个焊盘电接触; 导电层，其设置在所述第二基板的所述上半导体层上并电连接到所述下半导体层与所述至少一个焊盘电接触的部分; 从上半导体层向下半导体层延伸并延伸到下半导体层的开口; 以及设置在所述上​​半导体层和所述导电层上的保护层，其中所述保护层延伸到所述开口的侧壁的一部分上，并且不覆盖所述开口中的下半导体层。

公开(公告)号：US20130207240A1

公开(公告)日：2013-08-15

申请号：US13829802

申请日：2013-03-14

Applicant: XINTEC INC.

Inventor： Hung-Jen LEE ,  Shu-Ming CHANG ,  Chen-Han CHIANG ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L23/544

CPC classification number: H01L23/544 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/13 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2223/5446 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/131 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29124 ,  H01L2224/2957 ,  H01L2224/296 ,  H01L2224/3003 ,  H01L2224/30155 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83125 ,  H01L2224/83127 ,  H01L2224/83192 ,  H01L2224/83895 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/00

Abstract: An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defined thereon, wherein the predetermined scribe lines define a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively and a cutting support structure located on peripheries of the chip support rings, and the spacing layer has a gap pattern separating the cutting support structure from the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure.

Abstract translation: 本发明的一个实施例提供了一种芯片封装结构的制造方法，包括：提供具有限定在其上的多个预定划线的第一基板，其中，所述预定划线限定多个器件区域; 将第二基板接合到第一基板，其中间隔层设置在其间并且分别具有位于装置区域中的多个芯片支撑环和位于芯片支撑环的周边的切割支撑结构，并且间隔层具有 将切割支撑结构与芯片支撑环分离的间隙图案; 以及切割所述第一基板和所述第二基板以形成多个芯片封装。 本发明的另一个实施例提供一种芯片封装结构。

公开(公告)号：US20190273175A1

公开(公告)日：2019-09-05

申请号：US16291637

申请日：2019-03-04

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Po-Han LEE ,  Chien-Min LIN ,  Yi-Rong HO

IPC: H01L31/12 ,  H01L31/02 ,  H01L31/0203 ,  H01L31/0216 ,  H01L31/028 ,  H01L31/18

Abstract: A chip package includes a chip, a sidewall structure that has a first light-shielding layer, a second light-shielding layer, and a cover. The chip has a light emitter and a light receiver that are located on a top surface of the chip. The sidewall structure is located on the top surface of the chip and has two aperture areas. The light emitter and the light receiver are respectively located in the two aperture areas. The sidewall structure surrounds the light emitter and the light receiver, and at least one surface of the sidewall structure has the first light-shielding layer. The second light-shielding layer is located between the chip and the sidewall structure. The cover is located on a surface of the sidewall structure facing away from the chip, and at least covers the light receiver and the sidewall structure that surrounds the light receiver.

公开(公告)号：US20170271276A1

公开(公告)日：2017-09-21

申请号：US15461334

申请日：2017-03-16

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Chia-Sheng LIN ,  Po-Han LEE ,  Wei-Luen SUEN

IPC: H01L23/00 ,  H01L23/58 ,  H01L23/544

CPC classification number: H01L23/562 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/544 ,  H01L23/585 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/5446 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/13024

Abstract: A chip package including a substrate that has a first surface and a second surface opposite thereto is provided. The substrate includes a chip region and a scribe line region that extends along the edge of the chip region. The chip package further includes a dielectric layer disposed on the first surface of the substrate. The dielectric layer corresponding to the scribe line region has a through groove that extends along the extending direction of the scribe line region. A method of forming the chip package is also provided.

公开(公告)号：US20160379040A1

公开(公告)日：2016-12-29

申请号：US15177143

申请日：2016-06-08

Applicant: XINTEC INC.

Inventor： Shu-Ming CHANG ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: G06K9/00 ,  G06F3/041

CPC classification number: G06K9/00013 ,  G06F3/041 ,  G06F2203/04103

Abstract: This invention provides a touch panel-sensing chip package module complex, comprising: a touch panel with a first top surface and a first bottom surface opposite to each other, wherein the first bottom surface having a first cavity with a bottom wall surrounded by a sidewall; a color layer formed on the bottom wall and the first bottom surface adjacent to the cavity; and a chip scale sensing chip package module bonded to the cavity by the color layer formed on the bottom wall of the cavity.

Abstract translation: 本发明提供了一种触摸面板感测芯片封装模块复合体，包括：具有第一顶表面和彼此相对的第一底表面的触摸面板，其中所述第一底表面具有第一腔体，所述第一腔体具有被侧壁包围的底壁 ; 形成在所述底壁和与所述空腔相邻的所述第一底面的着色层; 以及通过形成在腔的底壁上的着色层与腔体结合的芯片尺度感测芯片封装模块。

公开(公告)号：US20160307779A1

公开(公告)日：2016-10-20

申请号：US15098278

申请日：2016-04-13

Applicant: XINTEC INC.

Inventor： Yu-Tung CHEN ,  Quan-Qun SU ,  Chuan-Jin SHIU ,  Chien-Hui CHEN ,  Hsiao-Lan YEH ,  Yen-Shih HO

IPC: H01L21/56 ,  H01L21/67 ,  B05B1/24 ,  H01L21/78 ,  H01L23/29 ,  H01L23/00 ,  H01L21/687 ,  H01L21/768

CPC classification number: H01L21/561 ,  H01L21/02118 ,  H01L21/02282 ,  H01L21/6715 ,  H01L21/68742 ,  H01L21/68764 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/11 ,  H01L24/94 ,  H01L2224/02313 ,  H01L2224/0346 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014

Abstract: A wafer coating system includes a wafer chuck, a flowing insulating material sprayer and a wafer tilting lifting pin. The wafer chuck has a carrier part and a rotating part, which the carrier part is mounted on the rotating part to carry a wafer, and the rotating part is configured to rotate with a predetermined axis. The flowing insulating material sprayer is above the wafer chuck and configured to spray a flowing insulating material to the wafer, and the wafer tilting lifting pin is configured to form a first acute angle between the wafer and direction of gravity.

Abstract translation: 晶片涂布系统包括晶片卡盘，流动绝缘材料喷雾器和晶片倾斜提升销。 晶片卡盘具有托架部和旋转部，托架部安装在旋转部上以承载晶片，旋转部构造成以预定轴旋转。 流动的绝缘材料喷雾器位于晶片卡盘之上，并配置成将流动的绝缘材料喷射到晶片上，并且晶片倾斜提升销构造成在晶片和重心之间形成第一锐角。

公开(公告)号：US20160218140A1

公开(公告)日：2016-07-28

申请号：US15086809

申请日：2016-03-31

Applicant: XINTEC INC.

Inventor： Wei-Ming CHIEN ,  Chia-Sheng LIN ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L27/146

CPC classification number: H01L27/14687 ,  H01L21/76898 ,  H01L27/14601 ,  H01L27/14636 ,  H01L33/62

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A patterned photoresist layer is formed on a wafer of the wafer structure. The wafer is etched, such that channels are formed in the wafer, and a protection layer of the wafer structure is exposed through the channels. The protection layer is etched, such that openings aligned with the channels are formed in the protection layer. Landing pads in the protection layer are respectively exposed through the openings and the channels, and the caliber of each of the openings is gradually increased toward the corresponding channel. Side surfaces of the wafer surrounding the channels are etched, such that the channels are expanded to respectively form hollow regions. The caliber of the hollow region is gradually decreased toward the opening, and the caliber of the opening is smaller than that of the hollow region.

Abstract translation: 半导体结构的制造方法包括以下步骤。 在晶片结构的晶片上形成图案化的光致抗蚀剂层。 蚀刻晶片，使得沟槽形成在晶片中，晶片结构的保护层通过沟道露出。 蚀刻保护层，使得在保护层中形成与沟道对准的开口。 保护层中的着陆垫分别通过开口和通道暴露，并且每个开口的口径朝着相应的通道逐渐增加。 蚀刻围绕通道的晶片的侧表面，使得通道膨胀以分别形成中空区域。 中空区域的口径朝向开口逐渐减小，并且开口的口径小于中空区域的口径。

公开(公告)号：US20150179831A1

公开(公告)日：2015-06-25

申请号：US14640307

申请日：2015-03-06

Applicant: XINTEC INC.

Inventor： Wei-Luen SUEN ,  Wei-Ming CHIEN ,  Po-Han LEE ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L31/0232 ,  H01L31/028 ,  H01L31/0236 ,  H01L31/02 ,  H01L31/0216 ,  H01L31/18

CPC classification number: H01L31/02327 ,  H01L21/561 ,  H01L23/3114 ,  H01L31/02002 ,  H01L31/0203 ,  H01L31/02363 ,  H01L31/1804 ,  H01L2224/11

Abstract: A semiconductor structure includes a silicon substrate, a protection layer, an electrical pad, an isolation layer, a redistribution layer, a conductive layer, a passivation layer, and a conductive structure. The silicon substrate has a concave region, a step structure, a tooth structure, a first surface, and a second surface opposite to the first surface. The step structure and the tooth structure surround the concave region. The step structure has a first oblique surface, a third surface, and a second oblique surface facing the concave region and connected in sequence. The protection layer is located on the first surface of the silicon substrate. The electrical pad is located in the protection layer and exposed through the concave region. The isolation layer is located on the first and second oblique surfaces, the second and third surfaces of the step structure, and the tooth structure.

Abstract translation: 半导体结构包括硅衬底，保护层，电焊盘，隔离层，再分配层，导电层，钝化层和导电结构。 硅基板具有凹形区域，台阶结构，齿结构，第一表面和与第一表面相对的第二表面。 台阶结构和齿结构围绕凹区域。 台阶结构具有第一倾斜表面，第三表面和面对凹入区域并且依次连接的第二倾斜表面。 保护层位于硅衬底的第一表面上。 电焊盘位于保护层中，并通过凹面露出。 隔离层位于第一和第二倾斜表面，台阶结构的第二和第三表面以及齿结构上。

公开(公告)号：US20150054002A1

公开(公告)日：2015-02-26

申请号：US14464570

申请日：2014-08-20

Applicant: XINTEC INC.

Inventor： Wei-Ming CHIEN ,  Chia-Sheng LIN ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L23/522 ,  H01L33/62 ,  H01L31/16

CPC classification number: H01L27/14687 ,  H01L21/76898 ,  H01L27/14601 ,  H01L27/14636 ,  H01L33/62

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A patterned photoresist layer is formed on a wafer of the wafer structure. The wafer is etched, such that channels are formed in the wafer, and a protection layer of the wafer structure is exposed through the channels. The protection layer is etched, such that openings aligned with the channels are formed in the protection layer. Landing pads in the protection layer are respectively exposed through the openings and the channels, and the caliber of each of the openings is gradually increased toward the corresponding channel. Side surfaces of the wafer surrounding the channels are etched, such that the channels are expanded to respectively form hollow regions. The caliber of the hollow region is gradually decreased toward the opening, and the caliber of the opening is smaller than that of the hollow region.

Abstract translation: 半导体结构的制造方法包括以下步骤。 在晶片结构的晶片上形成图案化的光致抗蚀剂层。 蚀刻晶片，使得沟槽形成在晶片中，晶片结构的保护层通过沟道露出。 蚀刻保护层，使得在保护层中形成与沟道对准的开口。 保护层中的着陆垫分别通过开口和通道暴露，并且每个开口的口径朝着相应的通道逐渐增加。 蚀刻围绕通道的晶片的侧表面，使得通道膨胀以分别形成中空区域。 中空区域的口径朝向开口逐渐减小，并且开口的口径小于中空区域的口径。