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公开(公告)号：US20160351608A1
公开(公告)日：2016-12-01
申请号：US15163625
申请日：2016-05-24
Applicant: XINTEC INC.
Inventor： Yu-Lung HUANG , Chi-Chang LIAO , Tsang-Yu LIU
IPC: H01L27/146
CPC classification number: H01L27/14623 , H01L27/14618 , H01L27/14636 , H01L27/14687 , H01L27/14698 , H01L2224/16 , H01L2924/16235
Abstract: A chip package includes a substrate, a conductive layer and a plurality of thermal dissipation connections. The substrate includes a light-sensing region and has an upper surface and a lower surface opposite to each other. The conductive layer is disposed at the lower surface of the substrate and includes a light-shielding dummy conductive layer substantially aligned with the light-sensing region. The thermal dissipation connections are disposed beneath the lower surface of the substrate.
Abstract translation: 芯片封装包括衬底，导电层和多个散热连接。 基板包括感光区域，并且具有彼此相对的上表面和下表面。 导电层设置在基板的下表面，并且包括基本上与光感测区域对准的遮光虚拟导电层。 散热连接设置在基板的下表面之下。
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公开(公告)号：US20160086896A1
公开(公告)日：2016-03-24
申请号：US14958155
申请日：2015-12-03
Applicant: XINTEC INC.
Inventor： Yu-Lung HUANG , Chao-Yen LIN , Wei-Luen SUEN , Chien-Hui CHEN
IPC: H01L23/58 , H01L21/78 , H01L21/283 , H01L21/48
CPC classification number: H01L23/585 , H01L21/283 , H01L21/4853 , H01L21/561 , H01L21/6836 , H01L21/768 , H01L21/78 , H01L23/3121 , H01L23/49838 , H01L23/525 , H01L24/05 , H01L24/16 , H01L24/48 , H01L29/0657 , H01L2221/68327 , H01L2221/6834 , H01L2224/02371 , H01L2224/02375 , H01L2224/02379 , H01L2224/02381 , H01L2224/0401 , H01L2224/04042 , H01L2224/05548 , H01L2224/05558 , H01L2224/06165 , H01L2224/06167 , H01L2224/1302 , H01L2224/131 , H01L2224/16105 , H01L2224/16225 , H01L2224/16227 , H01L2224/24226 , H01L2224/48091 , H01L2224/48227 , H01L2224/73215 , H01L2224/73253 , H01L2224/94 , H01L2924/00014 , H01L2924/10155 , H01L2924/10156 , H01L2924/10253 , H01L2924/12041 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/15788 , H01L2924/00 , H01L2224/03 , H01L2924/014 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
Abstract: An embodiment of the invention provides a chip package including a semiconductor substrate having a first surface and a second surface opposite thereto. A conducting pad is located on the first surface. A side recess is on at least a first side of the semiconductor substrate, wherein the side recess extends from the first surface toward the second surface and across the entire length of the first side. A conducting layer is located on the first surface and electrically connected to the conducting pad, wherein the conducting layer extends to the side recess.
Abstract translation: 本发明的实施例提供一种芯片封装，其包括具有第一表面和与其相对的第二表面的半导体衬底。 导电垫位于第一表面上。 侧凹部位于半导体衬底的至少第一侧上，其中侧凹部从第一表面朝向第二表面延伸并跨越第一侧的整个长度。 导电层位于第一表面上并电连接到导电焊盘，其中导电层延伸到侧凹槽。
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公开(公告)号：US20130292825A1
公开(公告)日：2013-11-07
申请号：US13887917
申请日：2013-05-06
Applicant: XINTEC INC.
Inventor： Yu-Lung HUANG , Tsang-Yu LIU , Shu-Ming CHANG
IPC: H01L23/498 , H01L21/78
CPC classification number: H01L23/49811 , B81B7/007 , B81B2207/092 , B81B2207/095 , H01L21/6836 , H01L21/76898 , H01L21/78 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2221/68327 , H01L2221/6834 , H01L2221/68372 , H01L2224/02372 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/13022 , H01L2224/13024 , H01L2224/13099 , H01L2224/94 , H01L2924/00014 , H01L2924/13091 , H01L2924/1461 , H01L2224/11 , H01L2224/03 , H01L2924/00 , H01L2224/05552
Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a device region formed in the semiconductor substrate; a dielectric layer disposed on the first surface of the semiconductor substrate; a conducting pad structure located in the dielectric layer and electrically connected to the device region, wherein the conducting pad structure comprises a stacked structure of a plurality of conducting pad layers; a support layer disposed on a top surface of the conducting pad structure; and a protection layer disposed on the second surface of the semiconductor substrate.
Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有第一表面和第二表面的半导体衬底; 形成在所述半导体衬底中的器件区域; 设置在所述半导体衬底的第一表面上的电介质层; 导电焊盘结构，其位于所述电介质层中并电连接到所述器件区域，其中所述导电焊盘结构包括多个导电焊盘层的堆叠结构; 支撑层，设置在所述导电焊盘结构的顶表面上; 以及设置在半导体衬底的第二表面上的保护层。
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公开(公告)号：US20170077158A1
公开(公告)日：2017-03-16
申请号：US15258594
申请日：2016-09-07
Applicant: XINTEC INC.
Inventor： Yu-Lung HUANG , Tsang-Yu LIU , Yi-Ming CHANG , Hsin KUAN
IPC: H01L27/146
CPC classification number: H01L27/14623 , H01L27/14618 , H01L27/14634 , H01L27/14685 , H01L2224/11
Abstract: A chip package including a substrate is provided. The substrate has a first surface and a second surface opposite thereto. The substrate includes a sensing region. A cover plate is on the first surface and covers the sensing region. A shielding layer covers a sidewall of the cover plate and extends towards the second surface. The shielding layer has an inner surface adjacent to the cover plate and has an outer surface away from the cover plate. The length of the outer surface extending towards the second surface is less than that of the inner surface extending towards the second surface, and is not less than that of the sidewall of the cover plate. A method of forming the chip package is also provided.
Abstract translation: 提供了包括基板的芯片封装。 基板具有与其相对的第一表面和第二表面。 衬底包括感测区域。 盖板在第一表面上并覆盖感测区域。 屏蔽层覆盖盖板的侧壁并朝向第二表面延伸。 屏蔽层具有与盖板相邻的内表面，并具有远离盖板的外表面。 朝向第二表面延伸的外表面的长度小于朝向第二表面延伸的内表面的长度，并且不小于盖板的侧壁的长度。 还提供了一种形成芯片封装的方法。
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公开(公告)号：US20170053848A1
公开(公告)日：2017-02-23
申请号：US15237287
申请日：2016-08-15
Applicant: XINTEC INC.
Inventor： Shu-Ming CHANG , Po-Chang HUANG , Tsang-Yu LIU , Yu-Lung HUANG , Chi-Chang LIAO
CPC classification number: H01L23/3121 , G06K9/00013 , G06K9/0002 , H01L23/3114 , H01L23/3178 , H01L23/481 , H01L2224/11
Abstract: A sensing module is provided. The sensing module includes a sensing device. The sensing device includes a first substrate having a first surface and a second surface opposite thereto. The sensing device also includes a sensing region adjacent to the first surface and a conducting pad on the first surface. The sensing device further includes a redistribution layer on the second surface and electrically connected to the conducting pad. The sensing module also includes a second substrate and a cover plate bonded to the sensing device so that the sensing device is between the second substrate and the cover plate. The conducting pad is electrically connected to the second substrate through the redistribution layer. The sensing module further includes an encapsulating layer filled between the second substrate and the cover plate to surround the sensing device.
Abstract translation: 提供感测模块。 感测模块包括感测装置。 感测装置包括具有第一表面和与其相对的第二表面的第一基底。 感测装置还包括与第一表面相邻的感测区域和第一表面上的导电垫片。 感测装置还包括在第二表面上的再分配层，并且电连接到导电垫。 感测模块还包括结合到感测装置的第二基板和盖板，使得感测装置在第二基板和盖板之间。 导电焊盘通过再分布层与第二基板电连接。 感测模块还包括填充在第二基板和盖板之间以封装感测装置的封装层。
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Patent Agency Ranking
公开(公告)号：US20140332983A1
公开(公告)日：2014-11-13
申请号：US14339341
申请日：2014-07-23
Applicant: XINTEC INC.
Inventor： Yen-Shih HO , Tsang-Yu LIU , Shu-Ming CHANG , Yu-Lung HUANG , Chao-Yen LIN , Wei-Luen SUEN , Chien-Hui CHEN
CPC classification number: H01L24/49 , G06K9/00053 , H01L21/561 , H01L23/3121 , H01L23/3192 , H01L23/525 , H01L23/5329 , H01L24/05 , H01L24/29 , H01L24/32 , H01L24/43 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/85 , H01L24/92 , H01L25/0657 , H01L29/0657 , H01L2224/02381 , H01L2224/024 , H01L2224/0401 , H01L2224/04042 , H01L2224/05548 , H01L2224/05554 , H01L2224/05558 , H01L2224/05567 , H01L2224/05572 , H01L2224/05611 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05669 , H01L2224/05687 , H01L2224/0569 , H01L2224/06135 , H01L2224/16225 , H01L2224/16227 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/43 , H01L2224/45144 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/48599 , H01L2224/48611 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/48655 , H01L2224/48669 , H01L2224/48687 , H01L2224/4869 , H01L2224/49113 , H01L2224/73265 , H01L2224/85 , H01L2224/92247 , H01L2224/94 , H01L2225/06506 , H01L2225/0651 , H01L2924/00014 , H01L2924/10155 , H01L2924/10156 , H01L2924/10253 , H01L2924/12041 , H01L2924/14 , H01L2924/146 , H01L2924/1461 , H01L2924/181 , H01L2224/03 , H01L2924/00 , H01L2924/00012 , H01L2224/05552
Abstract: A stacked chip package including a device substrate having an upper surface, a lower surface and a sidewall is provided. The device substrate includes a sensing region or device region, a signal pad region and a shallow recess structure extending from the upper surface toward the lower surface along the sidewall. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A wire has a first end disposed in the shallow recess structure and electrically connected to the redistribution layer, and a second end electrically connected to a first substrate and/or a second substrate disposed under the lower surface. A method for forming the stacked chip package is also provided.
Abstract translation: 提供了包括具有上表面，下表面和侧壁的器件衬底的堆叠芯片封装。 器件衬底包括感测区域或器件区域，信号焊盘区域和沿着侧壁从上表面向下表面延伸的浅凹陷结构。 再分配层电连接到信号焊盘区域并延伸到浅凹陷结构中。 电线具有设置在浅凹陷结构中并电连接到再分布层的第一端，以及电连接到设置在下表面下方的第一基板和/或第二基板的第二端。 还提供了一种用于形成堆叠芯片封装的方法。
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公开(公告)号：US20140332908A1
公开(公告)日：2014-11-13
申请号：US14339360
申请日：2014-07-23
Applicant: XINTEC INC.
Inventor： Yen-Shih HO , Tsang-Yu LIU , Shu-Ming CHANG , Yu-Lung HUANG , Chao-Yen LIN , Wei-Luen SUEN , Chien-Hui CHEN , Ho-Yin YIU
IPC: H01L23/48 , H01L21/56 , H01L21/768 , H01L23/00 , H01L23/31
CPC classification number: H01L21/76802 , G06K9/00053 , H01L21/561 , H01L21/76877 , H01L23/3121 , H01L23/3135 , H01L23/3192 , H01L23/525 , H01L23/5329 , H01L24/05 , H01L24/06 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2224/02166 , H01L2224/02381 , H01L2224/024 , H01L2224/04042 , H01L2224/05548 , H01L2224/05554 , H01L2224/05558 , H01L2224/05567 , H01L2224/05572 , H01L2224/05611 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05669 , H01L2224/05687 , H01L2224/0569 , H01L2224/06135 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/48611 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/48655 , H01L2224/48669 , H01L2224/48687 , H01L2224/4869 , H01L2224/73265 , H01L2224/8592 , H01L2224/94 , H01L2924/00014 , H01L2924/10155 , H01L2924/10156 , H01L2924/10253 , H01L2924/12041 , H01L2924/14 , H01L2924/1461 , H01L2924/181 , H01L2224/03 , H01L2924/00 , H01L2924/00012 , H01L2224/05552
Abstract: A chip package including a chip is provided. The chip includes a sensing region or device region adjacent to an upper surface of the chip. A sensing array is located in the sensing region or device region and includes a plurality of sensing units. A plurality of first openings is located in the chip and correspondingly exposes the sensing units. A plurality of conductive extending portions is disposed in the first openings and is electrically connected to the sensing units, wherein the conductive extending portions extend from the first openings onto the upper surface of the chip. A method for forming the chip package is also provided.
Abstract translation: 提供了包括芯片的芯片封装。 芯片包括与芯片的上表面相邻的感测区域或器件区域。 感测阵列位于感测区域或设备区域中并且包括多个感测单元。 多个第一开口位于芯片中并且相应地暴露感测单元。 多个导电延伸部分设置在第一开口中并且电连接到感测单元，其中导电延伸部分从第一开口延伸到芯片的上表面上。 还提供了一种用于形成芯片封装的方法。
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公开(公告)号：US20140154830A1
公开(公告)日：2014-06-05
申请号：US14173526
申请日：2014-02-05
Applicant: XINTEC INC
Inventor： Yu-Lung HUANG , Tzu-Hsiang HUNG , Yen-Shih HO
IPC: H01L31/18
CPC classification number: H01L31/1876 , H01L27/14618 , H01L27/14687 , H01L2224/13 , H01L2224/94
Abstract: A method for forming an image sensor chip package includes: providing a substrate having predetermined scribe lines defined thereon, wherein the predetermined scribe lines define device regions and each of the device regions has at least a device formed therein; disposing a support substrate on a first surface of the substrate; forming at least a spacer layer between the support substrate and the substrate, wherein the spacer layer covers the predetermined scribe lines; forming a package layer on a second surface of the substrate; forming conducting structures on the second surface of the substrate, wherein the conducting structures are electrically connected to the corresponding device in corresponding one of the device regions, respectively; and dicing along the predetermined scribe lines such that the support substrate is removed from the substrate and the substrate is separated into a plurality of individual image sensor chip packages.
Abstract translation: 一种用于形成图像传感器芯片封装的方法，包括：提供具有限定在其上的预定划线的基板，其中，所述预定划线限定器件区域，并且每个器件区域至少具有形成在其中的器件; 将支撑基板设置在所述基板的第一表面上; 在所述支撑基板和所述基板之间形成至少间隔层，其中所述间隔层覆盖所述预定划线; 在所述基板的第二表面上形成封装层; 在所述衬底的第二表面上形成导电结构，其中所述导电结构分别在相应的一个所述器件区域中电连接到相应的器件; 并且沿着预定的划线切割，使得支撑基板从基板移除，并且基板被分离成多个单独的图像传感器芯片封装。
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公开(公告)号：US20140065769A1
公开(公告)日：2014-03-06
申请号：US14074519
申请日：2013-11-07
Applicant: XINTEC INC.
Inventor： Yu-Lung HUANG , Tsang-Yu LIU
IPC: H01L23/00
CPC classification number: H01L24/94 , H01L23/3114 , H01L23/3171 , H01L27/14618 , H01L27/14627 , H01L31/048 , H01L2924/12041 , H01L2924/12042 , H01L2924/14 , H01L2924/1461 , H01L2924/15788 , H04N5/2257 , H01L2924/00
Abstract: An embodiment of the invention provides a chip package, which includes: a semiconductor substrate having a device region; a package layer disposed on the semiconductor substrate; a spacing layer disposed between the semiconductor substrate and the package layer and surrounding the device region; and an auxiliary pattern having a hollow pattern formed in the spacing layer, a material pattern located between the spacing layer and the device region, or combinations thereof.
Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有器件区域的半导体衬底; 封装层，设置在所述半导体衬底上; 间隔层，设置在所述半导体衬底和所述封装层之间并且围绕所述器件区域; 以及形成在间隔层中的中空图案的辅助图案，位于间隔层和器件区域之间的材料图案，或其组合。
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公开(公告)号：US20140054786A1
公开(公告)日：2014-02-27
申请号：US13964999
申请日：2013-08-12
Applicant: XINTEC INC.
Inventor： Yu-Lung HUANG , Chao-Yen LIN , Wei-Luen SUEN , Chien-Hui CHEN
IPC: H01L23/498 , H01L21/768
CPC classification number: H01L23/585 , H01L21/283 , H01L21/4853 , H01L21/561 , H01L21/6836 , H01L21/768 , H01L21/78 , H01L23/3121 , H01L23/49838 , H01L23/525 , H01L24/05 , H01L24/16 , H01L24/48 , H01L29/0657 , H01L2221/68327 , H01L2221/6834 , H01L2224/02371 , H01L2224/02375 , H01L2224/02379 , H01L2224/02381 , H01L2224/0401 , H01L2224/04042 , H01L2224/05548 , H01L2224/05558 , H01L2224/06165 , H01L2224/06167 , H01L2224/1302 , H01L2224/131 , H01L2224/16105 , H01L2224/16225 , H01L2224/16227 , H01L2224/24226 , H01L2224/48091 , H01L2224/48227 , H01L2224/73215 , H01L2224/73253 , H01L2224/94 , H01L2924/00014 , H01L2924/10155 , H01L2924/10156 , H01L2924/10253 , H01L2924/12041 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/15788 , H01L2924/00 , H01L2224/03 , H01L2924/014 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
Abstract: An embodiment of the invention provides a chip package including a semiconductor substrate having a first surface and a second surface opposite thereto. A conducting pad is located on the first surface. A side recess is on at least a first side of the semiconductor substrate, wherein the side recess extends from the first surface toward the second surface and across the entire length of the first side. A conducting layer is located on the first surface and electrically connected to the conducting pad, wherein the conducting layer extends to the side recess.
Abstract translation: 本发明的实施例提供一种芯片封装，其包括具有第一表面和与其相对的第二表面的半导体衬底。 导电垫位于第一表面上。 侧凹部位于半导体衬底的至少第一侧上，其中侧凹部从第一表面朝向第二表面延伸并跨越第一侧的整个长度。 导电层位于第一表面上并电连接到导电焊盘，其中导电层延伸到侧凹槽。
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