公开(公告)号：US11694949B2

公开(公告)日：2023-07-04

申请号：US16529194

申请日：2019-08-01

申请人： Samsung Electronics Co., Ltd.

发明人： Yun-Seok Choi

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L23/485

CPC分类号： H01L23/49816 ,  H01L21/486 ,  H01L21/4853 ,  H01L23/4855 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/33

摘要： A semiconductor package includes a package substrate, an interposer on the package substrate, and a first semiconductor device and a second semiconductor device on the interposer, the first and second semiconductor devices connected to each other by the interposer, wherein at least one of the first semiconductor device and the second semiconductor device includes an overhang portion protruding from a sidewall of the interposer.

公开(公告)号：US09633945B1

公开(公告)日：2017-04-25

申请号：US15171151

申请日：2016-06-02

申请人： Kabushiki Kaisha Toshiba

发明人： Takuya Mizutani

IPC分类号： H01L23/485 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522 ,  H01L21/768 ,  H01L23/538 ,  H01L25/065

CPC分类号： H01L21/76877 ,  H01L21/76816 ,  H01L23/4855 ,  H01L23/5226 ,  H01L23/5386 ,  H01L25/0657 ,  H01L27/1157 ,  H01L27/11582 ,  H01L28/00

摘要： According to one embodiment, there is provided a semiconductor device, which includes an electrode lead-out part, a planarization film, contacts, and first and second columnar patterns. The electrode lead-out part is arranged such that an electrode film and an insulating film are alternately stacked in a plurality of layers, and layers of the electrode film are arranged stepwise. The planarization film is arranged above the electrode lead-out part. The first columnar pattern extends from a lowermost portion of the electrode lead-out part to a position lower than the upper side of the planarization film by a first depth. The second columnar pattern extends from a lowermost portion of the electrode lead-out part to a position lower than the upper side of the planarization film by a second depth larger than the first depth.

公开(公告)号：US20130228924A1

公开(公告)日：2013-09-05

申请号：US13774228

申请日：2013-02-22

申请人： SKYWORKS SOLUTIONS, INC.

发明人： Kezia Cheng

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L23/53238 ,  H01L21/469 ,  H01L21/768 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76852 ,  H01L21/76895 ,  H01L21/8252 ,  H01L23/485 ,  H01L23/4855 ,  H01L23/5283 ,  H01L23/532 ,  H01L23/53223 ,  H01L23/535 ,  H01L23/66 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0605 ,  H01L29/41 ,  H01L29/452 ,  H01L29/475 ,  H01L2223/6677 ,  H01L2224/04042 ,  H01L2224/05666 ,  H01L2224/48463 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13063 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： Disclosed are devices and methods related to metallization of semiconductors. A metalized structure can include a first titanium (Ti) layer disposed over a compound semiconductor, a first barrier layer disposed over the first Ti layer, a second Ti layer disposed over the first barrier layer, and a copper (Cu) layer disposed over the second Ti layer. The second Ti layer can be configured to inhibit or reduce alloying of the Cu layer and the first barrier layer. The first Ti layer, the first barrier layer, and the second Ti layer can be configured to yield a barrier between the Cu layer and an ohmic metal layer formed on the compound semiconductor. The metalized structure can further include a third Ti layer disposed over the Cu layer and a second barrier layer disposed over the third Ti layer. The first and second barrier layers can include platinum (Pt) and/or palladium (Pd).

摘要翻译： 公开了与半导体的金属化相关的器件和方法。 金属化结构可以包括设置在化合物半导体上的第一钛（Ti）层，设置在第一Ti层上的第一势垒层，设置在第一阻挡层上的第二Ti层和设置在第一Ti层上的铜（Cu）层 第二Ti层。 第二Ti层可以被配置为抑制或减少Cu层和第一阻挡层的合金化。 第一Ti层，第一势垒层和第二Ti层可以被配置为在Cu层和形成在化合物半导体上的欧姆金属层之间产生阻挡层。 金属化结构还可包括设置在Cu层上的第三Ti层和设置在第三Ti层上的第二阻挡层。 第一和第二阻挡层可以包括铂（Pt）和/或钯（Pd）。

公开(公告)号：US5619069A

公开(公告)日：1997-04-08

申请号：US458655

申请日：1995-06-02

申请人： Hiroyuki Ohta ,  Hideo Miura ,  Hiroo Masuda ,  Yoichi Tamaki ,  Takahide Ikeda ,  Asao Nishimura ,  Takashi Hashimoto

发明人： Hiroyuki Ohta ,  Hideo Miura ,  Hiroo Masuda ,  Yoichi Tamaki ,  Takahide Ikeda ,  Asao Nishimura ,  Takashi Hashimoto

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L23/485 ,  H01L27/06 ,  H01L29/732 ,  H01L23/48

CPC分类号： H01L23/4855 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S148/01 ,  Y10S148/124 ,  Y10S148/135

摘要： A bipolar device having a level difference between the contact area level of a base electrode and a base region in a silicon substrate, and the contact area level of an emitter electrode and an emitter region in the silicon substrate in the range of 0.03 .mu.m to 0.1 .mu.m by removing undesirable impurities from the emitter region and a predetermined horizontal distance between a sidewall and a device isolation film does not generate dislocation and show good electric characteristics.

摘要翻译： 具有硅基板中的基极的接触面积电平与基极区域之间的电平差的硅双极器件，以及硅基板的发射电极和发射极区域的接触面积电平为0.03μm〜 通过从发射极区域去除不需要的杂质并且侧壁和器件隔离膜之间的预定水平距离不产生位错并且显示出良好的电特性，0.1μm。

公开(公告)号：US4809055A

公开(公告)日：1989-02-28

申请号：US191747

申请日：1988-05-05

申请人： Masaru Ishibashi ,  Takeshi Tsubata ,  Kazumi Sasaki

发明人： Masaru Ishibashi ,  Takeshi Tsubata ,  Kazumi Sasaki

IPC分类号： H01L29/73 ,  H01L21/28 ,  H01L21/331 ,  H01L23/485 ,  H01L23/532 ,  H01L29/732 ,  H01L23/54 ,  H01L23/14

CPC分类号： H01L23/53242 ,  H01L23/4855 ,  H01L2924/0002

摘要： An SiO.sub.2 insulating layer is formed on an Si substrate, and an Si.sub.3 N.sub.4 insulating layer is formed on the SiO.sub.2 layer. A notch is formed in the Si.sub.3 N.sub.4 layer using a resist film as a mask. The SiO.sub.2 layer is etched using the Si.sub.3 N.sub.4 layer as a mask, thereby forming an opening larger than the notch cut in the SiO.sub.2 layer. As a result, the Si.sub.3 N.sub.4 layer extends over the opening in an overhanging manner. When As.sup.+ ions are implanted in the periphery of the notch of the Si.sub.3 N.sub.4 layer, the ion-implanted portion of the Si.sub.3 N.sub.4 layer is arcuated toward the base region. When a metal such as Ti is deposited on the arcuated portion, the metal is also deposited on the arcuated portion and the portion of the emitter region matching with the notch, thereby forming an emitter electrode portion.

摘要翻译： 在Si衬底上形成SiO 2绝缘层，在SiO 2层上形成Si 3 N 4绝缘层。 使用抗蚀剂膜作为掩模在Si 3 N 4层中形成切口。 使用Si 3 N 4层作为掩模蚀刻SiO 2层，从而形成比在SiO 2层中切割的切口大的开口。 结果，Si 3 N 4层以突出的方式在开口上延伸。 当As +离子注入到Si 3 N 4层的凹口的周围时，Si 3 N 4层的离子注入部分朝向基极区域弧形化。 当诸如Ti的金属沉积在弧形部分上时，金属也沉积在弧形部分上，并且发射极区域的部分与凹口匹配，从而形成发射极电极部分。

公开(公告)号：US3839111A

公开(公告)日：1974-10-01

申请号：US38971873

申请日：1973-08-20

申请人： RCA CORP

发明人： HAM E ,  SODEN R

IPC分类号： H01L21/3205 ,  H01L21/00 ,  H01L21/306 ,  H01L21/311 ,  H01L23/29 ,  H01L23/485 ,  H01L23/522 ,  H01L7/50

CPC分类号： H01L23/293 ,  H01L21/00 ,  H01L21/31111 ,  H01L21/31144 ,  H01L23/4855 ,  H01L23/522 ,  H01L2924/0002 ,  Y10S438/978 ,  H01L2924/00

摘要： A method of etching away a selected portion of silicon oxide from a body of silicon oxide and tapering the edge of the remaining silicon oxide that delineates the selected portion comprises the steps of (a) delineating the selected portion with a coating of a photoresist on a surface of the body, and (b) etching away the selected portion with a composite solution that contains both an etchant for the silicon oxide and a component for lifting only the edge of the photoresist from the interface between the photoresist and the silicon oxide at the delineation of the selected portion.

摘要翻译： 蚀刻掉氧化硅体的选定部分的硅氧化物的方法，并使描绘所选择的部分的剩余氧化硅的边缘变细，包括以下步骤：（a）用光刻胶的涂层描绘所选择的部分 表面，以及（b）用复合溶液蚀刻所选择的部分，所述复合溶液既含有氧化硅的蚀刻剂，也包含仅在光致抗蚀剂和氧化硅之间的界面处提取光致抗蚀剂的边缘的组分 描绘所选部分。

公开(公告)号：US3837907A

公开(公告)日：1974-09-24

申请号：US23688672

申请日：1972-03-22

申请人： BELL TELEPHONE LABOR INC

发明人： BERGLUND C ,  WAGGENER H ,  NICOLLIAN E ,  TOMPSETT M

IPC分类号： H01L29/78 ,  H01L21/00 ,  H01L21/288 ,  H01L21/3205 ,  H01L21/339 ,  H01L21/60 ,  H01L23/29 ,  H01L23/485 ,  H01L29/423 ,  B44D1/18 ,  H01L5/02

CPC分类号： H01L21/76897 ,  H01L21/00 ,  H01L21/288 ,  H01L21/2885 ,  H01L23/291 ,  H01L23/4855 ,  H01L24/02 ,  H01L29/42396 ,  H01L29/66954 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/1306 ,  H01L2924/14 ,  Y10S438/944 ,  H01L2924/00

摘要： A method of forming multi-level metallization in integrated circuits with essentially zero effective lateral spacing between adjacent isolated metal portions. Indentations are formed at least partially through a first dielectric layer; and a second dielectric layer having apertures registered with and smaller than the indentations is formed thereover such that portions of the second layer overhang the indentations at the perimeters thereof. A thin metal layer then is deposited over the surface of the structure. Because the second dielectric layer overhangs the indentations, the deposited metal is discontinuous at the perimeter of each of the indentations if the deposited metal layer is kept sufficiently thin. Selective connection of adjacent metal portions at any portion of the perimeter of any indentation is made by any of a variety of techniques, such as electroless plating of gold through a photoresist mask.

摘要翻译： 在集成电路中形成多层金属化的方法，其中相邻隔离金属部分之间的有效横向间隔基本上为零。 至少部分地通过第一介电层形成压痕; 并且形成具有被记录有并且小于凹口的孔的第二电介质层，使得第二层的部分在其周边伸出凹陷。 然后将薄的金属层沉积在结构的表面上。 因为第二电介质层突出了凹陷，所以如果沉积的金属层保持足够薄，沉积的金属在每个凹槽的周边是不连续的。 通过各种技术中的任何一种，例如通过光致抗蚀剂掩模对金进行无电镀，可以选择性地连接任何压痕的周边任何部分处的相邻金属部分。

公开(公告)号：US20230290711A1

公开(公告)日：2023-09-14

申请号：US18318864

申请日：2023-05-17

申请人： Samsung Electronics Co., Ltd.

发明人： Yun-Seok CHOI

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L23/485

CPC分类号： H01L23/49816 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49838 ,  H01L23/49827 ,  H01L23/5386 ,  H01L24/33 ,  H01L23/4855

摘要： A semiconductor package includes a package substrate, an interposer on the package substrate, and a first semiconductor device and a second semiconductor device on the interposer, the first and second semiconductor devices connected to each other by the interposer, wherein at least one of the first semiconductor device and the second semiconductor device includes an overhang portion protruding from a sidewall of the interposer.

公开(公告)号：US20180331008A1

公开(公告)日：2018-11-15

申请号：US15970525

申请日：2018-05-03

申请人： ROHM CO., LTD.

发明人： Isamu NISHIMURA

IPC分类号： H01L23/34 ,  H01L23/10 ,  H01L23/49 ,  H01L23/485 ,  H01L23/28

CPC分类号： H01L23/34 ,  H01L23/10 ,  H01L23/28 ,  H01L23/3121 ,  H01L23/4855 ,  H01L23/49 ,  H01L33/58 ,  H01L33/62 ,  H01L33/64 ,  H01L2224/16

摘要： The present disclosure provides a semiconductor device for high efficiently releasing heat generated from a semiconductor element to the outside. The semiconductor device of the present disclosure includes a substrate, made of an intrinsic semiconductor material, having a substrate main surface facing toward a thickness direction z, and configured to have a recess recessed from the substrate main surface; an internal wiring layer, disposed on the substrate main surface and the recess; a columnar conductor, protruding from the internal wiring layer disposed on the substrate main surface toward a direction in which the substrate main surface faces; a semiconductor element, having an element main surface facing the same direction as the substrate main surface, and electrically connected to the internal wiring layer; and a sealing resin, filled into the recess and covering a portion of each of the columnar conductor and the semiconductor element; wherein the semiconductor element has a portion overlapping the recess when viewed in the thickness direction of the substrate, and the semiconductor device is configured to have a heat dissipating layer being in contact with the element main surface and exposed to the outside.

公开(公告)号：US20180005901A1

公开(公告)日：2018-01-04

申请号：US15196371

申请日：2016-06-29

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

发明人： Cheng Chi ,  Ruilong Xie

IPC分类号： H01L21/8238 ,  H01L23/522 ,  H01L29/417 ,  H01L23/528 ,  H01L23/485 ,  H01L21/311 ,  H01L29/66 ,  H01L27/12

CPC分类号： H01L23/5226 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/4855 ,  H01L23/5283 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66545

摘要： A method for forming a semiconductor device comprises forming a gate stack on a channel region of a semiconductor, forming a source/drain region adjacent to the channel region, depositing a first insulator layer over the source/drain region, and removing a portion of the first insulator layer to form a first cavity that exposes a portion of the source/drain region. A first conductive material is deposited in the first cavity, and a conductive extension is formed from the first conductive material over the first insulator layer. A protective layer is deposited over the extension and a second insulator layer is deposited over the protective layer. A portion of the second insulator layer is removed to form a second cavity that exposes the protective layer, and an exposed portion of the protective layer is removed to expose a portion of the extension. A second conductive material is deposited in the second cavity.