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    Dynamic system configuration based on cloud-collaborative experimentation
    191.
    发明授权
    Dynamic system configuration based on cloud-collaborative experimentation 有权

    公开(公告)号：US09755902B2

    公开(公告)日：2017-09-05

    申请号：US14474623

    申请日：2014-09-02

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： Wen-Chi Chen ,  Rodney E. Hooker

    IPC: H04L12/24 ,  G06F15/177

    CPC classification number: H04L41/0833 ,  G06F15/177 ,  H04L41/0806

    Abstract: A server includes a first module that receives information from a plurality of systems. Each system of the plurality of systems includes functional units that are dynamically configurable during operation of the system. The information from each system of the plurality of systems includes performance data collected while executing a program when the functional units are configured according to a configuration setting respective to the system. The server also includes a second module that analyzes the received information to select a best-performing configuration setting of the configuration settings received from the plurality of systems. The server also includes a third module that provides a new configuration setting to the plurality of systems. The new configuration setting is a modification of the best-performing configuration. The server iterates on receiving the information from the plurality of systems, analyzing the received information and providing the new configuration setting to the plurality of systems.

    Natural language comprehension system
    192.
    发明授权
    Natural language comprehension system 有权

    公开(公告)号：US09715524B1

    公开(公告)日：2017-07-25

    申请号：US15462926

    申请日：2017-03-20

    Applicant: VIA Technologies, Inc.

    Inventor： Guo-Feng Zhang ,  Yi-Fei Zhu

    IPC: G06F17/30 ,  G06F17/27

    CPC classification number: G06F17/28 ,  G06F17/2705 ,  G06F17/271 ,  G06F17/2785 ,  G06F17/30312 ,  G06F17/30401 ,  G06F17/30864

    Abstract: A search method, a search system, and a natural language comprehension system are provided. The search system includes a structured database and a search engine. The structured database stores a plurality of records, each of which has a title field and a content field. The title field includes at least one sub-field, and each sub-field includes an indication field and a value field. The indication field stores indication data, the value field stores value data, and the content field stores detailed content data. The search engine conducts a full-text search to the records in the structured database according to a keyword derived from a user's request formation, and a search result is transmitted to a knowledge comprehension assistance module, so as to recognize the user's intention. After the user's intention is recognized, information associated with the recognized user's intention is transmitted back to the user.

    FUSE-ENABLED SECURE BIOS MECHANISM WITH OVERRIDE FEATURE
    195.
    发明申请
    FUSE-ENABLED SECURE BIOS MECHANISM WITH OVERRIDE FEATURE 有权

    公开(公告)号：US20170046517A1

    公开(公告)日：2017-02-16

    申请号：US15338620

    申请日：2016-10-31

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： G. GLENN HENRY

    IPC: G06F21/57 ,  G06F21/78 ,  H04L9/06

    CPC classification number: G06F21/572 ,  G06F21/78 ,  G06F2221/2139 ,  H04L9/0631 ,  H04L9/0643

    Abstract: An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), a tamper detector, a random number generator, a JTAG control chain, a fuse, a machine specific register, and an access controller. The BIOS ROM includes BIOS contents stored as plaintext, and an encrypted message digest, where the encrypted message digest has an encrypted version of a first message digest that corresponds to the BIOS contents. The tamper detector is operatively coupled to the BIOS ROM, and is configured to generate a BIOS check interrupt at a combination of prescribed intervals and event occurrences, and is configured to access the BIOS contents and the encrypted message digest upon assertion of the BIOS check interrupt, and is configured to direct a microprocessor to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest, and is configured to compare the second message digest with the decrypted message digest, and is configured to preclude the operation of the microprocessor if the second message digest and the decrypted message digest are not equal. The random number generator disposed within the microprocessor, and generates a random number at completion of a current BIOS check, which is employed to set a following prescribed interval, whereby the prescribed intervals are randomly varied. The JTAG control chain is configured to program the combination of prescribed intervals and event occurrences within tamper detection microcode storage. The fuse is configured to indicate whether programming of the combination of prescribed intervals and event occurrences is to be disabled. The machine specific register is configured to store a value therein. The access control element is coupled to the fuse, the machine specific register, and the JTAG control chain, and is configured to determine that the fuse is blown, and configured to direct the JTAG control chain to enable programming of the combination of prescribed intervals and event occurrences if the value matches an override value within the access control element during a period that the value is stored within the machine specific register.

    Selective prefetching of physically sequential cache line to cache line that includes loaded page table entry
    196.
    发明授权
    Selective prefetching of physically sequential cache line to cache line that includes loaded page table entry 有权
    将物理顺序高速缓存行选择性预取到包含加载的页表条目的高速缓存行

    公开(公告)号：US09569363B2

    公开(公告)日：2017-02-14

    申请号：US14790467

    申请日：2015-07-02

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： Rodney E. Hooker ,  Colin Eddy

    IPC: G06F12/08 ,  G06F12/10

    CPC classification number: G06F12/0862 ,  G06F12/10 ,  G06F12/1027 ,  G06F2212/1024 ,  G06F2212/251 ,  G06F2212/6022 ,  G06F2212/6028 ,  G06F2212/684 ,  G06F2212/654

    Abstract: A microprocessor includes a translation lookaside buffer and a first request to load into the microprocessor a page table entry in response to a miss of a virtual address in the translation lookaside buffer. The requested page table entry is included in a page table. The page table encompasses a plurality of cache lines including a first cache line that includes the requested page table entry. The microprocessor also includes hardware logic that makes a determination whether a second cache line physically sequential to the first cache line is outside the page table, and a second request to prefetch the second cache line into the microprocessor. The second request is selectively generated based at least on the determination made by the hardware logic.

    Abstract translation: 微处理器包括翻译后备缓冲器和响应于翻译后备缓冲器中的虚拟地址的缺失而将微处理器加载到页表条目的第一请求。 请求的页表项包含在页表中。 该页表包含多条高速缓存行，包括包含所请求的页表项的第一高速缓存行。 微处理器还包括硬件逻辑，其确定与第一高速缓存行物理连续的第二高速缓存线是否在页表之外，以及将第二高速缓存线预取到微处理器中的第二请求。 至少基于硬件逻辑的判定来选择性地生成第二请求。

    Source synchronous data strobe misalignment compensation mechanism
    197.
    发明授权
    Source synchronous data strobe misalignment compensation mechanism 有权
    源同步数据选通偏移补偿机制

    公开(公告)号：US09552320B2

    公开(公告)日：2017-01-24

    申请号：US13747038

    申请日：2013-01-22

    Applicant: VIA Technologies, Inc.

    Inventor： Vanessa S. Canac ,  James R. Lundberg

    IPC: G06F13/42

    CPC classification number: G06F13/4243 ,  G06F1/12 ,  G06F13/4217 ,  G11C7/1072 ,  G11C8/18

    Abstract: A method that compensates for misalignment on a synchronous data bus. The method includes: replicating propagation path lengths, loads, and buffering of a radial distribution network for a strobe, receiving a lag pulse signal, and generating a replicated strobe signal by employing the replicated propagation path loads lengths, and buffering; measuring the time between assertion of the lag pulse signal and assertion of the replicated strobe signal; on a lag bus, generating a value that indicates the time; within a synchronous lag receiver, receiving a first one of a plurality of radially distributed strobes and a data bit, and delaying registering of the data bit by the time.

    Abstract translation: 补偿同步数据总线上的未对准的方法。 该方法包括：复制用于选通的径向分布网络的传播路径长度，负载和缓冲，接收延迟脉冲信号，以及通过采用复制的传播路径负载长度和缓冲来产生复制的选通信号; 测量滞后脉冲信号的断言与复制的选通信号的断言之间的时间; 在滞后总线上产生一个表示时间的值; 在同步延迟接收器内，接收多个径向分布的选通信号中的第一个选通信号和数据位，并延迟数据位的记录。

    CONTROL CHIP AND CONTROL SYSTEM UTILIZING THE SAME
    198.
    发明申请
    CONTROL CHIP AND CONTROL SYSTEM UTILIZING THE SAME 审中-公开
    使用其控制芯片和控制系统

    公开(公告)号：US20170005648A1

    公开(公告)日：2017-01-05

    申请号：US14877509

    申请日：2015-10-07

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： Hao-Hsuan CHIU ,  Yen-Ting LAI

    IPC: H03K17/00

    CPC classification number: H03K17/002

    Abstract: A control chip coupled to a first input/output pin and a second input/output pin and including a first interface module, a second interface module, a first switching unit, and a control unit is provided. The first interface module includes a first pin electrically connected to the first input/output pin and a second pin. The second interface module includes a third pin. The control unit controls the first switching unit to turn on a first path between the second pin and the second input/output pin or a second path between the third pin and the second input/output pin. When the first path is turned on, the first interface module controls the voltage levels of the first and second input/output pins. When the second path is turned on, the second interface module controls the voltage level of the second input/output pin.

    Abstract translation: 提供了耦合到第一输入/输出引脚和第二输入/输出引脚并且包括第一接口模块，第二接口模块，第一开关单元和控制单元的控制芯片。 第一接口模块包括电连接到第一输入/输出引脚和第二引脚的第一引脚。 第二接口模块包括第三引脚。 控制单元控制第一切换单元打开第二引脚和第二输入/输出引脚之间的第一路径或第三引脚与第二输入/输出引脚之间的第二路径。 当第一路径被接通时，第一接口模块控制第一和第二输入/输出引脚的电压电平。 当第二路径被打开时，第二接口模块控制第二输入/输出引脚的电压电平。

    Circuit substrate
    200.
    发明授权
    Circuit substrate 有权
    电路基板

    公开(公告)号：US09532467B2

    公开(公告)日：2016-12-27

    申请号：US14020104

    申请日：2013-09-06

    Applicant: VIA Technologies, Inc.

    Inventor： Chen-Yueh Kung

    IPC: H05K3/46 ,  H05K1/02 ,  H05K3/04 ,  H05K3/10

    CPC classification number: H05K3/465 ,  H05K1/0298 ,  H05K3/045 ,  H05K3/108 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2203/0554 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

    Abstract: A circuit substrate includes a base layer, a first patterned conductive layer, a dielectric layer, a conductive block and a second patterned conductive layer. The first patterned conductive layer is disposed on the base layer and has a first pad. The dielectric layer is disposed on the base layer and covers the first patterned conductive layer, wherein the dielectric layer has an opening and the first pad is exposed by the opening. The conductive block is disposed in the opening and covers the first pad. The second patterned conductive layer is disposed on a surface of the dielectric layer and has a second pad, wherein the second pad and the conductive block are integrally formed.

    Abstract translation: 电路基板包括基底层，第一图案化导电层，电介质层，导电块和第二图案化导电层。 第一图案化导电层设置在基底层上并具有第一焊盘。 电介质层设置在基底层上并覆盖第一图案化导电层，其中电介质层具有开口，第一焊盘由开口露出。 导电块设置在开口中并覆盖第一焊盘。 第二图案化导电层设置在电介质层的表面上并具有第二焊盘，其中第二焊盘和导电块一体形成。

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