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    Methods of forming fins for FinFET semiconductor devices and the resulting devices
    232.
    发明授权
    Methods of forming fins for FinFET semiconductor devices and the resulting devices 有权
    形成FinFET半导体器件的翅片的方法和所得到的器件

    公开(公告)号：US09449881B1

    公开(公告)日：2016-09-20

    申请号：US14710053

    申请日：2015-05-12

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Min Gyu Sung ,  Ruilong Xie

    IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/308 ,  H01L21/764 ,  H01L21/762 ,  H01L21/3105 ,  H01L29/66

    CPC classification number: H01L21/823431 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/823821 ,  H01L29/66795 ,  H01L29/6681

    Abstract: A method includes forming a plurality of fins above a substrate, forming at least one dielectric material above and between the plurality of fins, and forming a mask layer above the dielectric material. The mask layer has an opening defined therein. At least one etching process is performed to remove a portion of the at least one dielectric material exposed by the opening so as to expose a top surface portion and sidewall surface portions of at least one fin in the plurality of fins. The at least one dielectric material remains above the substrate adjacent the at least one fin. An etching process is performed to remove the at least one fin.

    Abstract translation: 一种方法包括在衬底上形成多个翅片，在多个翅片之上和之间形成至少一种电介质材料，并在电介质材料之上形成掩模层。 掩模层具有限定在其中的开口。 执行至少一个蚀刻工艺以去除由开口暴露的至少一个介电材料的一部分，以暴露多个翅片中的至少一个翅片的顶表面部分和侧壁表面部分。 所述至少一个介电材料保留在与所述至少一个翅片相邻的衬底上。 进行蚀刻处理以去除至少一个翅片。

    Interconnect structures and methods of fabrication
    233.
    发明授权
    Interconnect structures and methods of fabrication 有权
    互连结构和制造方法

    公开(公告)号：US09412695B1

    公开(公告)日：2016-08-09

    申请号：US14641699

    申请日：2015-03-09

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Hiroaki Niimi ,  Andreas Knorr

    IPC: H01L23/52 ,  H01L23/528 ,  H01L21/768 ,  H01L29/66 ,  H01L29/423 ,  H01L21/311 ,  H01L21/32 ,  H01L29/78 ,  H01L23/535 ,  H01L23/532

    CPC classification number: H01L29/7851 ,  H01L21/28525 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/42364 ,  H01L29/66795

    Abstract: Methods and interconnect structures for circuit structure transistors are provided. The methods include, for instance: providing one or more fins above a substrate, and an insulating material over the fin(s) and the substrate; providing barrier structures extending into the insulating material, the barrier structures being disposed along opposing sides of the fin(s); exposing a portion of the fin(s) and the barrier structures; and forming an interconnect structure extending over the fin(s), the barrier structures confining the interconnect structure to a defined dimension transverse to the fin(s). Exposing the portion of the fin(s) and barrier structures may include isotropically etching the insulating material with an etchant that selectively etches the insulating material without affecting a barrier material of the barrier structures.

    Abstract translation: 提供了用于电路结构晶体管的方法和互连结构。 所述方法包括例如：在衬底上提供一个或多个鳍片，以及在鳍片和衬底上方的绝缘材料; 提供延伸到所述绝缘材料中的阻挡结构，所述阻挡结构沿着所述鳍片的相对侧布置; 暴露所述鳍片和所述屏障结构的一部分; 以及形成在所述翅片上延伸的互连结构，所述阻挡结构将所述互连结构限制在横向于所述鳍片的限定尺寸。 暴露鳍状物和阻挡结构的部分可以包括用蚀刻剂均匀地蚀刻绝缘材料，该蚀刻剂选择性地蚀刻绝缘材料而不影响阻挡结构的阻挡材料。

    Methods of forming single and double diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products
    234.
    发明授权
    Methods of forming single and double diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products 有权
    在由FinFET器件和所得产品组成的集成电路产品上形成单次和双重扩散断裂的方法

    公开(公告)号：US09412616B1

    公开(公告)日：2016-08-09

    申请号：US14942448

    申请日：2015-11-16

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Kwan-Yong Lim ,  Min Gyu Sung ,  Ryan Ryoung-Han Kim

    IPC: H01L21/00 ,  H01L21/3105 ,  H01L21/027 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/283 ,  H01L21/762

    CPC classification number: H01L29/66545 ,  H01L21/76224 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

    Abstract: One illustrative method disclosed herein includes, among other things, forming a multi-layer patterned masking layer comprised of first and second layers of material and first and second openings that extend through both of the first and second layers of material, wherein the first opening is positioned above a first area of the substrate where the DDB isolation structure will be formed and the second opening is positioned above a second area of the substrate where the SDB isolation structure will be formed. The method also includes performing a first process operation through the first opening to form the DDB isolation structure, performing a second process operation to remove the second layer of material and to expose the first opening in the first layer of material, and performing a third process operation through the second opening to form the SDB isolation structure.

    Abstract translation: 本文公开的一种说明性方法包括形成由第一和第二层材料构成的多层图案化掩模层，以及延伸穿过第一和第二材料层的第一和第二开口，其中第一开口是 位于基板的将形成DDB隔离结构的第一区域之上，并且第二开口位于衬底的将形成SDB隔离结构的第二区域之上。 该方法还包括通过第一开口执行第一处理操作以形成DDB隔离结构，执行第二处理操作以去除第二层材料并露出第一层材料中的第一开口，以及执行第三工艺 通过第二次开启操作形成SDB隔离结构。

    Method of uniform fin recessing using isotropic etch
    236.
    发明授权
    Method of uniform fin recessing using isotropic etch 有权
    使用各向同性蚀刻均匀翅片凹陷的方法

    公开(公告)号：US09391174B1

    公开(公告)日：2016-07-12

    申请号：US14730735

    申请日：2015-06-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Min Gyu Sung ,  Ruilong Xie ,  Chanro Park ,  Hoon Kim

    IPC: H01L29/66 ,  H01L21/306 ,  H01L21/31 ,  H01L21/311

    CPC classification number: H01L29/66795 ,  H01L21/3083

    Abstract: Uniform fin recessing for the situation of recessing nonadjacent fins and the situation of recessing adjacent fins includes providing a starting semiconductor structure, the structure including a semiconductor substrate, multiple fins coupled to the substrate, each fin having a hard mask layer thereover and being surrounded by isolation material. The hard mask layer is then removed over some of the fins, at least partially removing the some of the raised structures, the at least partially removing creating openings, and filling the openings with an optical planarization layer (OPL) material.

    Abstract translation: 针对不相邻散热片的凹陷状况的均匀的翅片凹陷以及相邻散热片的凹陷情况包括提供起始半导体结构，该结构包括半导体衬底，耦合到衬底的多个鳍片，每个散热片具有其上的硬掩模层并被 隔离材料。 然后在一些翅片上去除硬掩模层，至少部分地去除一些凸起结构，至少部分去除创建开口，并用光学平坦化层（OPL）材料填充开口。

    METHODS OF FORMING REPLACEMENT GATE STRUCTURES FOR SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES
    239.
    发明申请
    METHODS OF FORMING REPLACEMENT GATE STRUCTURES FOR SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES 有权
    形成半导体器件和结果器件替代门结构的方法

    公开(公告)号：US20160163601A1

    公开(公告)日：2016-06-09

    申请号：US14560102

    申请日：2014-12-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Chanro Park ,  Sean Xuan Lin

    IPC: H01L21/8234 ,  H01L21/3213 ,  H01L27/088 ,  H01L29/51 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L21/02

    CPC classification number: H01L21/823468 ,  H01L21/02181 ,  H01L21/28088 ,  H01L21/32133 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628

    Abstract: A method that involves forming a high-k gate insulation layer, a work-function adjusting metal layer and a metal protection layer in first and second replacement gate cavities, wherein the metal protection layer is formed so as to pinch-off the first gate cavity while leaving the second gate cavity partially un-filled, forming a first bulk conductive metal layer in the un-filled portion of the second gate cavity, removing substantially all of the metal protection layer in the first gate cavity while leaving a portion of the metal protection layer in the second gate cavity, forming a second conductive metal layer within the first and second replacement gate cavities, recessing the conductive metal layers so as to define first and second gate-cap cavities in the first and second replacement gate cavities, respectively, and forming gate cap layers within the first and second gate-cap cavities.

    Abstract translation: 一种涉及在第一和第二替换栅腔中形成高k栅极绝缘层，功函数调整金属层和金属保护层的方法，其中金属保护层形成为夹住第一栅极腔 同时使第二栅极腔部分未填充，在第二栅极腔的未填充部分中形成第一体导电金属层，基本上除去第一栅极腔中的所有金属保护层，同时留下金属的一部分 在所述第二栅极腔中形成保护层，在所述第一和第二替代栅极腔内形成第二导电金属层，使所述导电金属层凹陷，以分别在所述第一和第二替换栅极腔中限定第一和第二栅极盖腔， 以及在所述第一和第二栅极盖腔内形成栅极盖层。

    METHODS OF FORMING SELF-ALIGNED CONTACT STRUCTURES ON SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES
    240.
    发明申请
    METHODS OF FORMING SELF-ALIGNED CONTACT STRUCTURES ON SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES 有权
    在半导体器件和结构器件上形成自对准接触结构的方法

    公开(公告)号：US20160163585A1

    公开(公告)日：2016-06-09

    申请号：US14674460

    申请日：2015-03-31

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Andre Labonte

    IPC: H01L21/768 ,  H01L29/45 ,  H01L29/417 ,  H01L21/283 ,  H01L29/66

    CPC classification number: H01L21/76843 ,  H01L21/283 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66628

    Abstract: One method disclosed includes, among other things, forming a structure comprised of an island of a first insulating material positioned between the gate structures above the source/drain region and under a masking layer feature of a patterned masking layer, forming a liner layer that contacts the island of insulating material and the masking layer feature, selectively removing the masking layer feature to thereby form an initial opening that is defined by the liner layer, performing at least one isotropic etching process through the initial opening to remove the island of first insulating material and thereby define a contact opening that exposes the source/drain region, and forming a conductive contact structure in the contact opening that is conductively coupled to the source/drain region.

    Abstract translation: 所公开的一种方法包括形成由位于源/漏区之上的栅极结构之间的第一绝缘材料的岛和图案化掩模层的掩模层特征之下的一个结构，形成接触 绝缘材料岛和掩模层特征，选择性地去除掩模层特征，从而形成由衬里层限定的初始开口，通过初始开口进行至少一个各向同性蚀刻工艺以去除第一绝缘材料岛 从而限定暴露源极/漏极区域的接触开口，以及在与源极/漏极区域导电耦合的接触开口中形成导电接触结构。

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