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62 条记录 (耗时 0.016 秒)

    CHIP-SIZED PACKAGE AND FABRICATION METHOD THEREOF
    22.
    发明申请
    CHIP-SIZED PACKAGE AND FABRICATION METHOD THEREOF 审中-公开
    芯片尺寸的封装及其制造方法

    公开(公告)号：US20120001328A1

    公开(公告)日：2012-01-05

    申请号：US12967844

    申请日：2010-12-14

    申请人： Chiang-Cheng Chang ,  Chien-Ping Huang ,  Chun-Chi Ke

    发明人： Chiang-Cheng Chang ,  Chien-Ping Huang ,  Chun-Chi Ke

    IPC分类号： H01L23/498 ,  H01L21/78

    CPC分类号： H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

    摘要： A chip-sized package and a fabrication method thereof are provided. The method includes forming a protection layer on an active surface of a chip and attaching a non-active surface of the chip to a carrier made of a hard material; performing a molding process and removing a protection layer from the chip; performing an RDL process to prevent problems as encountered in the prior art, such as softening of adhesive films, an encapsulant overflow, a pliable chip and chip deviation or contamination caused by directly adhering the active surface of the chip to the adhesive film that may even lead to inferior electrical contacts between a circuit layer and a plurality of chip bond pads during subsequent RDL process, and cause the package to be scraped. Further, the carrier employed in this invention can be repetitively used in the process to help reduce manufacturing costs.

    摘要翻译： 提供了一种芯片尺寸的封装及其制造方法。 该方法包括在芯片的有源表面上形成保护层，并将芯片的非活性表面附着到由硬质材料制成的载体上; 执行模制过程并从芯片去除保护层; 执行RDL处理以防止现有技术中遇到的问题，例如粘合剂膜的软化，密封剂溢出，柔韧的芯片和芯片偏差或由将芯片的活性表面直接粘附到甚至可能粘合的粘合剂膜引起的污染 在随后的RDL处理期间导致电路层和多个芯片接合焊盘之间的较差的电接触，并导致封装被刮除。 此外，本发明中使用的载体可以在该过程中重复使用以帮助降低制造成本。

    Semiconductor package and method for fabricating the same
    25.
    发明申请
    Semiconductor package and method for fabricating the same 审中-公开
    半导体封装及其制造方法

    公开(公告)号：US20090102063A1

    公开(公告)日：2009-04-23

    申请号：US12287936

    申请日：2008-10-14

    申请人： Chun-Yuan Lee ,  Chien Ping Huang ,  Yu-Ting Lai ,  Cheng-Hsu Hsiao ,  Chun-Chi Ke

    发明人： Chun-Yuan Lee ,  Chien Ping Huang ,  Yu-Ting Lai ,  Cheng-Hsu Hsiao ,  Chun-Chi Ke

    IPC分类号： H01L23/48 ,  H01L21/00

    CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/48 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： This invention provides a semiconductor package and a method for fabricating the same. The method includes: forming a first resist layer on a metal carrier; forming a plurality of openings penetrating the first resist layer; forming a conductive metal layer in the openings; removing the first resist layer; covering the metal carrier having the conductive metal layer with a dielectric layer; forming blind vias in the dielectric layer to expose a portion of the conductive metal layer; forming conductive circuit on the dielectric layer and conductive posts in the blind vias, such that the conductive circuit is electrically connected to the conductive metal layer via the conductive posts; electrically connecting at least one chip to the conductive circuit; forming an encapsulant for encapsulating the chip and the conductive circuit; and removing the metal carrier, thereby allowing a semiconductor package to be formed without a chip carrier. Given the conductive posts, both the conductive circuit and conductive metal layer are efficiently coupled to the dielectric layer to prevent delamination. Further, downsizing the blind vias facilitates the fabrication process and cuts the fabrication cost.

    摘要翻译： 本发明提供一种半导体封装及其制造方法。 该方法包括：在金属载体上形成第一抗蚀剂层; 形成穿过所述第一抗蚀剂层的多个开口; 在所述开口中形成导电金属层; 去除第一抗蚀剂层; 用介电层覆盖具有导电金属层的金属载体; 在介电层中形成盲孔以暴露导电金属层的一部分; 在介电层上形成导电电路和在盲孔中的导电柱，使得导电电路经由导电柱电连接到导电金属层; 将至少一个芯片电连接到所述导电电路; 形成用于封装所述芯片和所述导电电路的密封剂; 并且去除金属载体，从而允许在没有芯片载体的情况下形成半导体封装。 给定导电柱，导电电路和导电金属层都有效地耦合到电介质层以防止分层。 此外，缩小盲孔通孔有助于制造工艺并降低制造成本。

    Fabrication method of under bump metallurgy structure
    28.
    发明申请
    Fabrication method of under bump metallurgy structure 有权
    凸块冶金结构的制造方法

    公开(公告)号：US20060252245A1

    公开(公告)日：2006-11-09

    申请号：US11190271

    申请日：2005-07-26

    申请人： Chun-Chi Ke ,  Chien-Ping Huang

    发明人： Chun-Chi Ke ,  Chien-Ping Huang

    IPC分类号： H01L21/44

    CPC分类号： H01L24/03 ,  H01L2224/0401 ,  H01L2224/73204 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014

    摘要： A fabrication method of under bump metallurgy (UBM) structure is provided. A blocking layer is applied over a surface of a semiconductor element formed with at least one bond pad and a passivation layer thereon. The passivation layer covers the semiconductor element and exposes the bond pad, and the blocking layer covers the bond pad and the passivation layer. The blocking layer is formed with at least one opening at a position corresponding to the bond pad. Metallic layers are formed on a surface of the blocking layer and at the opening. The metallic layers are patterned to form a UBM structure at the opening corresponding to the bond pad. Then the blocking layer is removed. The blocking layer can separate the metallic layers for forming the UBM structure from the passivation layer to prevent metallic residues of the UBM structure from being left on the passivation layer.

    摘要翻译： 提供了一种凸块下冶金（UBM）结构的制造方法。 在其上形成有至少一个接合焊盘和钝化层的半导体元件的表面上施加阻挡层。 钝化层覆盖半导体元件并暴露接合焊盘，并且阻挡层覆盖接合焊盘和钝化层。 阻挡层在对应于接合焊盘的位置处形成有至少一个开口。 金属层形成在阻挡层的表面和开口处。 金属层被图案化以在对应于接合焊盘的开口处形成UBM结构。 然后去除阻挡层。 阻挡层可以将用于形成UBM结构的金属层与钝化层分开，以防止UBM结构的金属残留物残留在钝化层上。

    Flash-preventing semiconductor package
    29.
    发明授权
    Flash-preventing semiconductor package 失效
    防闪光半导体封装

    公开(公告)号：US06864564B2

    公开(公告)日：2005-03-08

    申请号：US10039219

    申请日：2002-01-02

    申请人： Chun-Chi Ke ,  Randy H. Y. Lo ,  ChiChuan Wu

    发明人： Chun-Chi Ke ,  Randy H. Y. Lo ,  ChiChuan Wu

    IPC分类号： H01L23/057 ,  H01L23/10 ,  H01L23/495 ,  H01L23/498 ,  H01L23/12

    CPC分类号： H01L23/10 ,  H01L23/057 ,  H01L23/49541 ,  H01L23/49558 ,  H01L23/49861 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/01079 ,  H01L2924/16195 ,  H01L2924/00014 ,  H01L2924/00

    摘要： A semiconductor package and a method for fabricating the same are proposed, in which a lead frame is modified to form protrusions at sides of middle portions of leads to reduce spacing between the adjacent middle portions. This allows resin flow to slow down in speed during molding and reduces area available for resin flashes occurring thereon, so as to effectively eliminate the occurrence of resin flashes on the leads. Moreover, tapes can be adhered onto the lead frame for covering spacing between adjacent leads of the lead frame; this further helps prevent resin flashes from occurrence. In such an environment free of resin flashes, die-bonding and wire-bonding processes can be proceeded smoothly with assurance of quality and reliability of fabricated semiconductor packages.

    摘要翻译： 提出了一种半导体封装及其制造方法，其中引线框架被修改以在引线的中间部分的侧面处形成突起，以减小相邻中间部分之间的间隔。 这允许树脂流动在模制期间降低速度并且减少可用于其上发生的树脂闪光的面积，以便有效地消除引线上树脂闪光的发生。 此外，可以将带子粘附到引线框架上以覆盖引线框架的相邻引线之间的间隔; 这进一步有助于防止树脂闪光发生。 在这种没有树脂闪光的环境中，可以顺利地进行芯片接合和引线接合工艺，同时保证制造的半导体封装的质量和可靠性。

    Package structure having micro-electromechanical element
    30.
    发明授权
    Package structure having micro-electromechanical element 有权
    具有微机电元件的封装结构

    公开(公告)号：US08564115B2

    公开(公告)日：2013-10-22

    申请号：US13492220

    申请日：2012-06-08

    申请人： Chang-Yueh Chan ,  Chien-Ping Huang ,  Chun-Chi Ke ,  Chun-An Huang ,  Chih-Ming Huang

    发明人： Chang-Yueh Chan ,  Chien-Ping Huang ,  Chun-Chi Ke ,  Chun-An Huang ,  Chih-Ming Huang

    IPC分类号： H01L23/04

    CPC分类号： H01L21/02 ,  B81B7/007 ,  B81B2207/07 ,  H01L23/52 ,  H01L29/84 ,  H01L2224/02166 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

    摘要： Proposed is a package structure having a micro-electromechanical (MEMS) element, including a chip having a plurality of electrical connecting pads and a MEMS element formed thereon; a lid disposed on the chip for covering the MEMS element; a stud bump disposed on each of the electrical connecting pads; an encapsulant formed on the chip with part of the stud bumps being exposed from the encapsulant; and a metal conductive layer formed on the encapsulant and connected to the stud bumps. The invention is characterized by completing the packaging process on the wafer directly to enable thinner and cheaper package structures to be fabricated within less time. This invention further provides a method for fabricating the package structure as described above.

    摘要翻译： 提出具有微机电（MEMS）元件的封装结构，其包括具有多个电连接焊盘和形成在其上的MEMS元件的芯片; 设置在所述芯片上用于覆盖所述MEMS元件的盖; 设置在每个电连接焊盘上的螺柱凸块; 形成在芯片上的密封剂，其中一部分柱状凸块从密封剂暴露出来; 以及金属导电层，形成在密封剂上并连接到凸块上。 本发明的特征在于直接完成晶片上的封装工艺，以便在更短的时间内制造更薄和更便宜的封装结构。 本发明还提供如上所述的用于制造封装结构的方法。