公开(公告)号：US20160172027A1

公开(公告)日：2016-06-16

申请号：US14571949

申请日：2014-12-16

Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

Inventor： Ehsan Tahmasebian ,  Hyoung Seub Rhie ,  Peter Gillingham

IPC: G11C13/00 ,  H01L51/00 ,  H01L51/10

CPC classification number: G11C13/0016 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C2013/0054 ,  G11C2213/34 ,  G11C2213/56 ,  G11C2213/72 ,  G11C2213/73 ,  G11C2213/74 ,  G11C2213/79 ,  G11C2213/82 ,  H01L51/0595

Abstract: A integrated circuit device with a polymer memory array includes active circuits formed in lower layers of a multi-level interconnect structure and a semiconductor substrate and also includes an array of polymer memory cells formed in an upper interconnect level having a plurality of cell node electrodes and source line electrodes for the polymer memory array, each polymer memory cell including a passive layer having at least one conductivity-facilitating compound that is formed on top and sidewall surfaces of a source line electrode, and an active layer having an impedance state that can change that is formed on top and sidewall surfaces of an adjacent cell node electrode with sufficient thickness to make direct physical contact with the passive layer.

Abstract translation: 具有聚合物存储器阵列的集成电路器件包括形成在多层互连结构的下层中的有源电路和半导体衬底，并且还包括形成在具有多个单元节点电极的上部互连电平中的聚合物存储器单元的阵列， 用于聚合物存储器阵列的源极线电极，每个聚合物存储单元包括具有形成在源极线电极的顶壁和侧壁表面上的至少一种导电性促进化合物的钝化层，以及具有可改变的阻抗状态的有源层 其形成在相邻电池节点电极的顶壁和侧壁表面上，具有足够的厚度以与被动层直接物理接触。

公开(公告)号：US09350349B2

公开(公告)日：2016-05-24

申请号：US14480143

申请日：2014-09-08

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Barry A. Hoberman ,  Daniel L. Hillman ,  William G. Walker ,  John M. Callahan ,  Michael A. Zampaglione ,  Andrew Cole

IPC: H03K19/17 ,  H03K19/003 ,  G11C5/14 ,  H03K3/356 ,  H03K17/10 ,  H03K19/00 ,  H03K5/14

CPC classification number: H03K19/0016 ,  G11C5/14 ,  G11C5/144 ,  G11C5/148 ,  H02M3/07 ,  H03K3/0372 ,  H03K3/356086 ,  H03K3/356113 ,  H03K5/14 ,  H03K17/102 ,  H03K19/00315

Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.

公开(公告)号：US09300291B2

公开(公告)日：2016-03-29

申请号：US14499275

申请日：2014-09-29

Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

Inventor： Bruce Millar

IPC: H03K17/16 ,  H03K19/003 ,  H03K19/00 ,  G11C5/06 ,  G11C7/02 ,  G11C7/10 ,  G11C11/4093 ,  H03H7/38 ,  H04L25/02 ,  H03H17/00

CPC classification number: H03K19/0005 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C11/4093 ,  G11C2207/2254 ,  H03H7/38 ,  H03H17/0045 ,  H04L25/0278 ,  H04L25/028

Abstract: A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination.

Abstract translation: 提供了执行片外驱动（OCD）和片上终端（ODT）的系统和方法。 由晶体管组成的公共上拉网络和由晶体管组成的公共下拉网络被采用来实现这两个功能。 在驱动模式下，上拉网络被配置为当要产生“开”输出时产生校准的驱动阻抗，并且当“关”输出为“关”时，上拉网络被配置为产生校准的驱动阻抗 生成。 在终端模式中，上拉网络和下拉网络被配置为分别产生校准的上拉电阻和下拉电阻，使得它们一起形成分离终端。

公开(公告)号：US09252205B2

公开(公告)日：2016-02-02

申请号：US14611501

申请日：2015-02-02

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Hyoung Seub Rhie

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/10855 ,  H01L27/108 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10873 ,  H01L28/90 ,  H01L28/91

Abstract: A high capacitance embedded capacitor and associated fabrication processes are disclosed for fabricating a capacitor stack in a multi-layer stack to include a first capacitor plate conductor formed with a cylinder-shaped storage node electrode formed in the multi-layer stack, a capacitor dielectric layer surrounding the cylinder-shaped storage node electrode, and a second capacitor plate conductor formed from a conductive layer in the multi-layer stack that is sandwiched between a bottom and top dielectric layer, where the cylinder-shaped storage node electrode is surrounded by and extends through the conductive layer.

Abstract translation: 公开了一种高电容嵌入式电容器和相关联的制造工艺，用于制造多层堆叠中的电容器堆叠，以包括形成有形成在多层堆叠中的圆柱形存储节点电极的第一电容器板导体，电容器介电层 围绕所述圆筒形存储节点电极的第二电容器板导体，以及由所述多层叠层中的导电层形成的第二电容器板导体，所述第二电容器板导体夹在所述底部和顶部电介质层之间，其中所述圆柱形存储节点电极被所述第一和第 通过导电层。

公开(公告)号：US20150364207A1

公开(公告)日：2015-12-17

申请号：US14753500

申请日：2015-06-29

Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

Inventor： Jin-Ki KIM

IPC: G11C16/34

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11521 ,  H01L27/11524

Abstract: A NAND flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where NAND cell strings connected to the same bitline are formed in at least two well sectors. At least one well sector can be selectively coupled to an erase voltage during an erase operation, such that unselected well sectors are inhibited from receiving the erase voltage. When the area of the well sectors decrease, a corresponding decrease in the capacitance of each well sector results. Accordingly, higher speed erasing of the NAND flash memory cells relative to a single well memory bank is obtained when the charge pump circuit drive capacity remains unchanged. Alternately, a constant erase speed corresponding to a single well memory bank is obtained by matching a well segment having a specific area to a charge pump with reduced drive capacity. A reduced drive capacity charge pump will occupy less semiconductor chip area, thereby reducing cost.

公开(公告)号：US20150303210A1

公开(公告)日：2015-10-22

申请号：US14699831

申请日：2015-04-29

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Hyoung Seub Rhie

IPC: H01L27/115 ,  H01L23/528 ,  G11C16/26

CPC classification number: H01L27/11556 ,  G11C7/18 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11531 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A flash memory device comprising a local sensing circuitry is provided in a hierarchical structure with local and global bit lines. The local sensing circuitry comprise read and pass circuits configured to sense and amplify read currents during read operations, wherein the amplified read signals may be passed to a global circuit via the local and global bit lines.

Abstract translation: 包括本地感测电路的闪速存储器件以具有局部和全局位线的分级结构提供。 本地感测电路包括被配置为在读取操作期间感测和放大读取电流的读取和通过电路，其中放大的读取信号可以经由本地和全局位线被传递到全局电路。

公开(公告)号：US09123394B2

公开(公告)日：2015-09-01

申请号：US14519759

申请日：2014-10-21

Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

Inventor： Byoung Jin Choi

IPC: G11C5/06 ,  G11C11/4097 ,  G11C11/4076 ,  G11C11/408 ,  G11C7/10 ,  G11C29/02

CPC classification number: H01L25/0657 ,  G11C5/06 ,  G11C7/10 ,  G11C7/1066 ,  G11C7/1093 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4097 ,  G11C29/023 ,  G11C29/028 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and apparatus for organizing memory for a computer system including a plurality of memory devices, connected to a logic device, particularly a memory system having a plurality of stacked memory dice connected to a logic die, with the logic device having capability to analyze and compensate for differing delays to the stacked devices stacking multiple dice divided into partitions serviced by multiple buses connected to a logic die, to increase throughput between the devices and logic device allowing large scale integration of memory with self-healing capability.

Abstract translation: 一种用于组织包括连接到逻辑设备的多个存储器设备的计算机系统的存储器的方法和装置，特别是具有连接到逻辑管芯的多个堆叠存储器管芯的存储器系统，该逻辑器件具有分析能力， 补偿堆叠设备的不同延迟，堆叠多个骰子被分成由连接到逻辑管芯的多个总线所服务的分区，以增加设备和逻辑设备之间的吞吐量，从而允许具有自愈能力的存储器的大规模集成。

公开(公告)号：US20150102461A1

公开(公告)日：2015-04-16

申请号：US14496797

申请日：2014-09-25

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Soogeun Lee

IPC: H01L27/108 ,  H01L49/02 ,  H01L23/532

CPC classification number: H01L27/10844 ,  H01L21/76844 ,  H01L21/76865 ,  H01L23/5223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/108 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/75 ,  H01L28/87 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A high capacitance embedded metal interconnect capacitor and associated fabrication processes are disclosed for using a directional barrier metal formation sequence in a dual damascene copper process to form multi-layer stacked copper interconnect structure having reduced barrier metal layer formation at the bottom of each via hole so that the multi-layer stacked copper interconnect structure may be readily removed and replaced with high capacitance MIM capacitor layers.

Abstract translation: 公开了一种高电容嵌入式金属互连电容器和相关的制造工艺，用于在双镶嵌铜工艺中使用方向性阻挡金属形成顺序，以形成在每个通孔底部形成减少的阻挡金属层的多层堆叠铜互连结构， 可以容易地去除多层堆叠铜互连结构并用高电容MIM电容器层代替。

公开(公告)号：US20150082072A1

公开(公告)日：2015-03-19

申请号：US14486484

申请日：2014-09-15

Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

Inventor： Hong Beom PYEON

IPC: G06F1/10

CPC classification number: G06F1/10 ,  G11C5/025 ,  G11C7/02 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/20 ,  G11C7/22 ,  G11C7/222 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H04L7/0008 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A system includes a memory controller and a plurality of memory devices that are connected in-series to the memory controller. The system operation is synchronous with clock that is provided in a fashion of source synchronous clock structure. The source synchronous clock structure includes a PLL (Phase-Locked Loop) that reshapes an incoming clock and a reshaped clock is provided. The PLL provides a shifted clock in phase of 90°. The phase-shifted clock and data are transmitted from the first device to the second device. Clock phase shift provides a center-edge clock with data to be transmitted. The devices are assigned with unique IDs. The least significant bit of the ID number of the last device is used for determination of clock alignment: edge- or center-aligned clock with data produced by the memory controller.

公开(公告)号：US20150081155A1

公开(公告)日：2015-03-19

申请号：US14553244

申请日：2014-11-25

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Nicolas Louis Bouchon

IPC: B60K6/46 ,  B60W30/192 ,  B60W10/06 ,  B60W10/08 ,  B60K6/547 ,  B60W10/115

CPC classification number: B60W20/30 ,  B60K6/46 ,  B60K6/48 ,  B60K6/543 ,  B60K6/547 ,  B60L15/2054 ,  B60L50/16 ,  B60L50/40 ,  B60L58/12 ,  B60L58/21 ,  B60L2200/12 ,  B60L2210/40 ,  B60L2220/12 ,  B60L2220/16 ,  B60L2240/12 ,  B60L2240/421 ,  B60L2240/423 ,  B60L2240/441 ,  B60L2240/443 ,  B60L2240/486 ,  B60L2240/507 ,  B60L2240/80 ,  B60L2260/26 ,  B60L2270/145 ,  B60W10/02 ,  B60W10/06 ,  B60W10/08 ,  B60W10/10 ,  B60W10/101 ,  B60W10/11 ,  B60W10/115 ,  B60W20/00 ,  B60W20/10 ,  B60W30/192 ,  B60W2510/0695 ,  B60W2510/081 ,  B60W2510/244 ,  B60W2520/10 ,  B60W2710/021 ,  B60W2710/025 ,  B60W2710/081 ,  B60W2710/1005 ,  B60W2720/10 ,  B60Y2200/92 ,  B60Y2300/192 ,  B60Y2300/42 ,  B60Y2300/43 ,  B60Y2300/50 ,  B60Y2300/60 ,  B60Y2400/70 ,  B60Y2400/72 ,  Y02T10/6221 ,  Y02T10/6286 ,  Y02T10/645 ,  Y02T10/70 ,  Y02T10/7005 ,  Y02T10/7022 ,  Y02T10/7044 ,  Y02T10/7061 ,  Y02T10/7077 ,  Y02T10/7241 ,  Y02T10/7275 ,  Y10S903/918 ,  Y10S903/919 ,  Y10S903/93 ,  Y10T477/23 ,  Y10T477/641 ,  Y10T477/656

Abstract: A method and apparatus for starting an engine in a hybrid vehicle being driven by an electric motor is disclosed. The motor is operably configured to deliver mechanical power through an automatic transmission to at least one vehicle drive wheel to cause an acceleration of the vehicle. The method involves coupling the engine to the motor to cause an inertial load on the motor thus causing the motor to decelerate to a reduced rotational speed to provide a starting torque to the engine for starting the engine, and causing the automatic transmission to change gear ratio to a target gear ratio associated with the reduced rotational speed while causing the motor to decelerate, the motor being operable to deliver increased torque at the reduced rotational speed, thereby generally maintaining the acceleration of the vehicle.

Abstract translation: 公开了一种用于启动由电动机驱动的混合动力车辆中的发动机的方法和装置。 马达被可操作地构造成通过自动变速器将机械动力输送到至少一个车辆驱动轮以引起车辆的加速。 该方法包括将发动机耦合到电动机以在电动机上引起惯性负载，从而使电动机减速到降低的转速，以向起动发动机的发动机提供起动转矩，并使自动变速器改变变速比 达到在使电机减速的同时降低转速的目标传动比，电动机可操作以在降低的转速下传递增加的扭矩，从而通常保持车辆的加速度。