公开(公告)号：US06574859B2

公开(公告)日：2003-06-10

申请号：US09785787

申请日：2001-02-16

Applicant: Shaji Farooq ,  Mario J. Interrante ,  Sudipta K. Ray ,  William E. Sablinski

Inventor： Shaji Farooq ,  Mario J. Interrante ,  Sudipta K. Ray ,  William E. Sablinski

IPC: H05K336

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/19105 ,  H05K3/3436 ,  H05K3/3463 ,  H05K3/3484 ,  H05K2201/0215 ,  H05K2201/0272 ,  H05K2201/094 ,  H05K2201/10992 ,  H05K2203/041 ,  H05K2203/0415 ,  Y02P70/613 ,  Y10T29/49126 ,  H01L2924/00

Abstract: An interconnection structure and methods for making and detaching the same are presented for column and ball grid array (CGA and BGA) structures by using a transient solder paste on the electronic module side of the interconnection that includes fine metal powder additives to increase the melting point of the solder bond. The metal powder additives change the composition of the solder bond such that the transient melting solder composition does not completely melt at temperatures below +230° C. and detach from the electronic module during subsequent ref lows. A Pb—Sn eutectic with a lower melting point is used on the opposite end of the interconnection structure. In the first method a transient melting solder paste is applied to the I/O pad of an electronic module by means of a screening mask. Interconnect structures are then bonded to the I/O pad. In a second method, solder preforms in a composition of the transient melting solder paste are wetted onto electronic module I/O pads and interconnect columns or balls are then bonded. Detachment of an electronic module from a circuit card can then be performed by heating the circuit card assembly to a temperature above the eutectic solder melting point, but below the transient solder joint melting point.

Abstract translation: 通过使用包括细金属粉末添加剂的电子模块侧的瞬态焊膏来提供柱和球栅阵列（CGA和BGA）结构的互连结构及其分离方法，以增加熔点 的焊点。 金属粉末添加剂改变焊料接合的组成，使得瞬态熔融焊料组合物在低于+ 230℃的温度下不会完全熔化，并且在后续参考低温期间与电子模块分离。 在互连结构的另一端使用具有较低熔点的Pb-Sn共晶体。在第一种方法中，通过掩模掩模将瞬态熔融焊膏施加到电子模块的I / O焊盘。 然后将互连结构结合到I / O焊盘。在第二种方法中，将瞬态熔融焊膏的组成中的焊料预成型件润湿到电子模块I / O焊盘上，然后连接互连柱或焊球。连接电子 然后可以通过将电路卡组件加热到高于共熔焊料熔点但低于瞬态焊点熔点的温度来执行电路卡的模块。

公开(公告)号：US06518674B2

公开(公告)日：2003-02-11

申请号：US09805596

申请日：2001-03-13

Applicant: Mario J. Interrante ,  Thomas E. Lombardi ,  Frank L. Pompeo ,  William E. Sablinski

Inventor： Mario J. Interrante ,  Thomas E. Lombardi ,  Frank L. Pompeo ,  William E. Sablinski

IPC: H01L2348

CPC classification number: H01L24/81 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H05K1/113 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/10992 ,  H05K2203/162 ,  H05K2203/176 ,  Y02P70/613 ,  H01L2924/00

Abstract: A temporary attach article of a first component to a second component which includes a first component having a first volume of a fusible material; a second component having a second volume of fusible material; and the first and second components being joined together through the first and second volumes of fusible material, wherein the first volume of fusible material has a melting point higher than a melting point of the second volume of fusible material so that the first and second components may be joined together without melting of the first volume of fusible material and wherein the second volume of fusible material is 5 to 20% of the first volume of fusible material. Also disclosed is a method for temporary attach of devices to an electronic substrate.

Abstract translation: 将第一部件临时附接到第二部件，其包括具有第一容积的可熔材料的第一部件; 具有第二容积的可熔材料的第二部件; 并且所述第一和第二部件通过所述第一和第二体积的可熔材料连接在一起，其中所述第一容积的可熔材料的熔点高于所述第二容积的可熔材料的熔点，使得所述第一和第二部件可以 在不熔化第一体积的可熔材料的情况下连接在一起，并且其中第二体积的可熔材料是第一体积的可熔材料的5至20％。 还公开了一种用于将设备临时附接到电子基板的方法。

公开(公告)号：US5945735A

公开(公告)日：1999-08-31

申请号：US797678

申请日：1997-01-31

Applicant: Laertis Economikos ,  Lester Wynn Herron ,  Mario J. Interrante

Inventor： Laertis Economikos ,  Lester Wynn Herron ,  Mario J. Interrante

IPC: H01L23/02 ,  H01L23/10 ,  H01L23/08 ,  H01L23/48

CPC classification number: H01L23/10 ,  H01L2224/16 ,  H01L2924/01067 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/16152 ,  H01L2924/163

Abstract: The present invention relates generally to a new process for hermetically sealing of a high thermally conductive substrate, such as, an aluminum nitride substrate, using a low thermally conductive interposer and structure thereof. More particularly, the invention encompasses a hermetic cap which is secured to an aluminum nitride substrate using the novel thermal interposer. The novel thermal interposer basically comprises of layers of relatively high thermal conductive metallic materials sandwiching a core layer of low thermal conductive metallic material.

公开(公告)号：US5478009A

公开(公告)日：1995-12-26

申请号：US288521

申请日：1994-08-10

Applicant: Mario J. Interrante ,  Laertis Economikos

Inventor： Mario J. Interrante ,  Laertis Economikos

IPC: B26F3/00 ,  B23K1/018 ,  B23K1/06 ,  B23K3/02 ,  H01L21/304 ,  H01L21/60 ,  H05K3/34 ,  H01L21/00

CPC classification number: B23K1/018 ,  B23K1/06 ,  Y10T225/10 ,  Y10T225/30

Abstract: A solder ball removal tool uses ultrasonic vibrations to remove specific solder balls from high density chips, substrate solder ball terminal connections, card or board solder ball connections, or other solder ball array for the purpose of customizing the electrical functionality of a module. The tool also allows for the removal of damaged or defective solder balls for the purpose of replacement with defect free solder balls.

Abstract translation: 焊球去除工具使用超声波振动来从高密度芯片，衬底焊球端子连接，卡或板焊球连接或其它焊球阵列去除特定的焊球，以便定制模块的电功能。 该工具还允许去除损坏或有缺陷的焊球，以更换无缺陷焊球。

公开(公告)号：US4634638A

公开(公告)日：1987-01-06

申请号：US331717

申请日：1981-12-17

Applicant: Norman G. Ainslie ,  Joseph M. Harvilchuck ,  Mario J. Interrante ,  William J. King, Jr. ,  Paul H. Palmateer ,  John F. Sullivan

Inventor： Norman G. Ainslie ,  Joseph M. Harvilchuck ,  Mario J. Interrante ,  William J. King, Jr. ,  Paul H. Palmateer ,  John F. Sullivan

IPC: C22C5/02 ,  B23K1/00 ,  B23K35/00 ,  B23K35/20 ,  B23K35/30 ,  H01L21/48 ,  H05K7/06

CPC classification number: B23K35/001 ,  B23K35/3013 ,  H01L21/4853 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  Y10T428/12882 ,  Y10T428/12889

Abstract: Brazing of elements to electronic chip carrying substrates requires brazing materials strong at high temperatures used to remove and replace chips. Flanges and pins are brazed with Au:Sn brazing alloys modified during brazing by addition of copper to the brazing material to promote formation of the higher melting point .beta. phase of the alloy and a Group VIII metal to draw Sn out of the melt by gettering, also to promote formation of the .beta. phase of the alloy and to thicken the braze material. A copper preform is plated with Ni and juxtaposed with surfaces to be brazed and the brazing material to add Ni and copper to the melt.

Abstract translation: 元件对电子芯片承载基板的钎焊需要在高温下使用硬钎焊材料去除和替换芯片。 法兰和引脚钎焊Au：Sn钎焊合金，在钎焊过程中加入铜，以钎焊材料，以促进合金的较高熔点β相的形成和第VIII族金属，通过吸气将Sn从熔体中拉出， 也促进了合金的β相的形成，并增加了钎焊材料。 铜预制件镀有Ni并与待钎焊的表面并置，并且钎焊材料将Ni和铜添加到熔体中。

公开(公告)号：US20130015579A1

公开(公告)日：2013-01-17

申请号：US13615804

申请日：2012-09-14

Applicant: Luc Guerin ,  Mario J. Interrante ,  Michael J. Shapiro ,  Thuy Tran-Quinn ,  Van T. Truong

Inventor： Luc Guerin ,  Mario J. Interrante ,  Michael J. Shapiro ,  Thuy Tran-Quinn ,  Van T. Truong

IPC: H01L23/488

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/03462 ,  H01L2224/03618 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0566 ,  H01L2224/05681 ,  H01L2224/10126 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/01026 ,  H01L2224/05552

Abstract: A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball.

Abstract translation: 焊球接触和制造焊球接触的方法包括：在集成电路（IC）芯片和金属焊盘上形成有通孔的第一绝缘层; 设置在所述通孔内和所述第一绝缘层的围绕所述通孔的部分上的凸块下冶金（UBM）结构; 第二绝缘层，形成在所述UBM结构的位于所述通孔的中心的外部的上表面上; 以及填充通孔并且设置在UBM结构的与通孔接触的内部的上表面上方的焊球，其中在焊球下面的UBM结构具有比焊球更大的直径。

公开(公告)号：US06762119B2

公开(公告)日：2004-07-13

申请号：US09885791

申请日：2001-06-20

Applicant: Sudipta K. Ray ,  Mitchell S. Cohen ,  Lester Wynn Herron ,  Mario J. Interrante ,  Thomas E. Lombardi ,  Subhash L. Shinde

Inventor： Sudipta K. Ray ,  Mitchell S. Cohen ,  Lester Wynn Herron ,  Mario J. Interrante ,  Thomas E. Lombardi ,  Subhash L. Shinde

IPC: H01L2144

CPC classification number: H01S5/02272 ,  G02B6/4238 ,  H01L24/45 ,  H01L2224/45144 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01S5/02236 ,  H01S5/02268 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A process and structure for forming an optical subassembly in an integrated circuit, comprising: defining electrically conducting lines and bonding pads in a metallization layer on a substrate; depositing a passivation layer over the metallization layer; etching the passivation layer to remove the passivation layer from each of the bonding pads and a portion of the metallization layer associated with each of the bonding pads; diffusing Cr from the lines proximate said bonding pads to prevent solder wetting down lines; bonding an optical device to one of the bonding pads; and attaching the substrate to a carrier utilizing solder bond attachment.

Abstract translation: 一种用于在集成电路中形成光学子组件的工艺和结构，包括：在衬底上的金属化层中限定导电线和焊盘; 在所述金属化层上沉积钝化层; 蚀刻钝化层以从每个接合焊盘和与每个焊盘相关联的金属化层的一部分去除钝化层; 从靠近所述接合焊盘的线扩散Cr，以防止焊料向下润湿; 将光学器件接合到所述接合焊盘之一; 以及使用焊料粘合附着将衬底附接到载体上。

公开(公告)号：US06740959B2

公开(公告)日：2004-05-25

申请号：US09921062

申请日：2001-08-01

Applicant: David James Alcoe ,  Jeffrey Thomas Coffin ,  Michael Anthony Gaynes ,  Harvey Charles Hamel ,  Mario J. Interrante ,  Brenda Lee Peterson ,  Megan J. Shannon ,  William Edward Sablinski ,  Christopher Todd Spring ,  Randall Joseph Stutzman ,  Renee L. Weisman ,  Jeffrey Allen Zitz

Inventor： David James Alcoe ,  Jeffrey Thomas Coffin ,  Michael Anthony Gaynes ,  Harvey Charles Hamel ,  Mario J. Interrante ,  Brenda Lee Peterson ,  Megan J. Shannon ,  William Edward Sablinski ,  Christopher Todd Spring ,  Randall Joseph Stutzman ,  Renee L. Weisman ,  Jeffrey Allen Zitz

IPC: H01L23552

CPC classification number: H01L23/552 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01087 ,  H01L2924/12044 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3025 ,  H01L2924/00

Abstract: Electronic packages incorporating EMI shielding, and particularly semiconductor devices which incorporate semiconductor chip-carrier structures having grounded bands embedded therein which are adapted to reduce outgoing and incident EMI emissions for high-speed switching electronic packages.

Abstract translation: 包括EMI屏蔽的电子封装，特别是包含嵌入其中具有接地带的半导体芯片 - 载体结构的半导体器件，其适于减少高速开关电子封装的输出和入射EMI发射。

公开(公告)号：US06429388B1

公开(公告)日：2002-08-06

申请号：US09564110

申请日：2000-05-03

Applicant: Mario J. Interrante ,  Brenda Peterson ,  Sudipta K. Ray ,  William E. Sablinski ,  Amit K. Sarkhel

Inventor： Mario J. Interrante ,  Brenda Peterson ,  Sudipta K. Ray ,  William E. Sablinski ,  Amit K. Sarkhel

IPC: H01R909

CPC classification number: B23K35/262 ,  H01L23/488 ,  H01L23/49811 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13109 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01322 ,  H05K3/3426 ,  H05K3/3436 ,  H05K3/3463 ,  H05K3/4015 ,  H05K2201/10242 ,  H05K2203/047 ,  Y02P70/613 ,  H01L2224/29099 ,  H01L2224/05599

Abstract: The present invention relates generally to a new semiconductor chip carrier connections, where the chip carrier and the second level assembly are made by a surface mount technology. More particularly, the invention encompasses surface mount technologies, such as, Ball Grid Array (BGA), Column Grid Array (CGA), to name a few, where the surface mount technology comprises essentially of a non-solder metallic connection, such as, a copper connection. The present invention is also related to Column Grid Array structures and process thereof.

Abstract translation: 本发明一般涉及新的半导体芯片载体连接，其中芯片载体和第二级组件是通过表面贴装技术制成的。 更具体地，本发明包括表面贴装技术，例如球栅阵列（BGA），柱栅阵列（CGA），其中表面贴装技术基本上由非焊料金属连接构成，例如， 铜连接。 本发明还涉及列格阵列结构及其工艺。

公开(公告)号：US06235996B1

公开(公告)日：2001-05-22

申请号：US09014804

申请日：1998-01-28

Applicant: Shaji Farooq ,  Mario J. Interrante ,  Sudipta K. Ray ,  William E. Sablinski

Inventor： Shaji Farooq ,  Mario J. Interrante ,  Sudipta K. Ray ,  William E. Sablinski

IPC: H01L2348

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/19105 ,  H05K3/3436 ,  H05K3/3463 ,  H05K3/3484 ,  H05K2201/0215 ,  H05K2201/0272 ,  H05K2201/094 ,  H05K2201/10992 ,  H05K2203/041 ,  H05K2203/0415 ,  Y02P70/613 ,  Y10T29/49126 ,  H01L2924/00

Abstract: An interconnection structure and methods for making and detaching the same are presented for column and ball grid array (CGA and BGA) structures by using a transient solder paste on the electronic module side of the interconnection that includes fine metal powder additives to increase the melting point of the solder bond. The metal powder additives change the composition of the solder bond such that the transient melting solder composition does not completely melt at temperatures below +230° C. and detach from the electronic module during subsequent reflows. A Pb—Sn eutectic with a lower melting point is used on the opposite end of the interconnection structure. In the first method a transient melting solder paste is applied to the I/O pad of an electronic module by a screening mask. Interconnect structures are then bonded to the I/O pad. In a second method, solder preforms in a composition of the transient melting solder paste are wetted onto electronic module I/O pads and interconnect columns or balls are then bonded. Detachment of an electronic module from a circuit card can then be performed by heating the circuit card assembly to a temperature above the eutectic solder melting point, but below the transient solder joint melting point.

Abstract translation: 通过使用包括细金属粉末添加剂的电子模块侧的瞬态焊膏来提供柱和球栅阵列（CGA和BGA）结构的互连结构及其分离方法，以增加熔点 的焊点。 金属粉末添加剂改变焊料接合的组成，使得瞬态熔融焊料组合物在低于+ 230℃的温度下不会完全熔化，并且在随后的回流期间与电子模块分离。 在互连结构的另一端使用具有较低熔点的Pb-Sn共晶体。 在第一种方法中，通过屏蔽掩模将瞬态熔融焊膏施加到电子模块的I / O焊盘。 然后将互连结构结合到I / O焊盘。 在第二种方法中，将瞬态熔融焊膏的组合物中的焊料预成型件润湿到电子模块I / O焊盘上，然后将互连柱或球接合。 然后可以通过将电路卡组件加热到高于共熔焊料熔点但低于瞬态焊点熔点的温度来执行从电路卡分离电子模块。