公开(公告)号：US08556157B2

公开(公告)日：2013-10-15

申请号：US13113305

申请日：2011-05-23

申请人： Seiki Sakuyama ,  Toshiya Akamatsu ,  Masateru Koide

发明人： Seiki Sakuyama ,  Toshiya Akamatsu ,  Masateru Koide

IPC分类号： B23K31/02

CPC分类号： H05K1/0271 ,  H01L21/4853 ,  H01L21/4867 ,  H01L21/563 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16506 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81805 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/3436 ,  H05K3/3463 ,  H05K3/3484 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/01083

摘要： A method of manufacturing an electronic apparatus including a first and a second components, includes: forming a first solder bump on one of the first component and the second component; forming a second solder bump on the other one of the first component and the second component; bringing the first solder bump into contact with the second solder bump at a temperature higher than the liquidus temperature of any of the first and the second solder bumps such that the first and the second solder bumps are fused together to form a solder joint of an alloy having a lower liquidus temperature than any of the first and the second solder bumps; and solidifying the solder joint between the first and the second component.

摘要翻译： 一种制造包括第一和第二部件的电子设备的方法，包括：在第一部件和第二部件之一上形成第一焊料凸块; 在所述第一部件和所述第二部件中的另一个上形成第二焊料凸块; 使得第一焊料凸点在比第一和第二焊料凸块中的任何一个的液相线温度高的温度下与第二焊料凸块接触，使得第一和第二焊料凸块熔合在一起以形成合金的焊接接头 具有比第一和第二焊料凸块中的任一个更低的液相线温度; 并固化第一和第二部件之间的焊接接头。

公开(公告)号：US08368230B2

公开(公告)日：2013-02-05

申请号：US12857893

申请日：2010-08-17

申请人： Masateru Koide

发明人： Masateru Koide

IPC分类号： H01L25/03

CPC分类号： H01L23/147 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L24/95 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/274 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81194 ,  H01L2224/81801 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05552

摘要： A multi-chip module includes a package board, a plurality of chips, and a wiring board. The plurality of chips are horizontally disposed on the package board. The plurality of chips are electrically connected with the package board, and respectively provided with via holes which penetrate through the plurality of chips. The plurality of chips are respectively provided with circuits at surfaces facing the package board. The wiring board is disposed on an opposite side to the package board across the plurality of chips. The wiring board includes a wiring pattern which is electrically connecting adjacent chips one another. The circuit is electrically connected to the wiring pattern through the via holes.

摘要翻译： 多芯片模块包括封装板，多个芯片和布线板。 多个芯片水平地设置在封装板上。 多个芯片与封装板电连接，并且分别设有穿过多个芯片的通孔。 多个芯片在面向封装板的表面处分别设置有电路。 布线板设置在多个芯片的与封装板相反的一侧。 布线板包括将相邻的芯片彼此电连接的布线图案。 电路通过通孔电连接到布线图案。

公开(公告)号：US20110044015A1

公开(公告)日：2011-02-24

申请号：US12852696

申请日：2010-08-09

申请人： Masateru KOIDE ,  Daisuke MIZUTANI

发明人： Masateru KOIDE ,  Daisuke MIZUTANI

IPC分类号： H05K7/02 ,  H05K3/36

CPC分类号： H01L23/147 ,  H01L23/373 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L25/0655 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15192 ,  H01L2924/15311 ,  Y10T29/49126 ,  H01L2924/00 ,  H01L2224/05599

摘要： A multichip module comprising: a base substrate; a wiring board disposed on the base substrate and having a wiring pattern; an adhesive layer configured to bond the base substrate to the wiring board while maintaining an electrical connection between the base substrate and the wiring board; and a plurality of chips connected to a surface of the wiring board, the surface being opposite the adhesive layer, wherein, assuming that α is a coefficient of thermal expansion of the wiring board, β is a coefficient of thermal expansion of the base substrate, and γ is a coefficient of thermal expansion of the adhesive layer, the relationship α

摘要翻译： 一种多芯片模块，包括：基底; 布线板，设置在基底基板上并具有布线图案; 粘合层，其被配置为将基底基板粘合到布线板，同时保持基底基板和布线板之间的电连接; 以及与所述布线板的表面连接的多个芯片，所述表面与所述粘合剂层相对，其中，假设所述布线基板的热膨胀系数α为αbgr; 是基材的热膨胀系数，γ是粘合剂层的热膨胀系数，α<γ<＆bgr; 满意

公开(公告)号：US20110042824A1

公开(公告)日：2011-02-24

申请号：US12857893

申请日：2010-08-17

申请人： Masateru KOIDE

发明人： Masateru KOIDE

IPC分类号： H01L23/538 ,  H01L21/60

CPC分类号： H01L23/147 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L24/95 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/274 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81194 ,  H01L2224/81801 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05552

摘要： A multi-chip module includes a package board, a plurality of chips, and a wiring board. The plurality of chips are horizontally disposed on the package board. The plurality of chips are electrically connected with the package board, and respectively provided with via holes which penetrate through the plurality of chips. The plurality of chips are respectively provided with circuits at surfaces facing the package board. The wiring board is disposed on an opposite side to the package board across the plurality of chips. The wiring board includes a wiring pattern which is electrically connecting adjacent chips one another. The circuit is electrically connected to the wiring pattern through the via holes.

摘要翻译： 多芯片模块包括封装板，多个芯片和布线板。 多个芯片水平地设置在封装板上。 多个芯片与封装板电连接，并且分别设有穿过多个芯片的通孔。 多个芯片在面向封装板的表面处分别设置有电路。 布线板设置在多个芯片的与封装板相反的一侧。 布线板包括将相邻的芯片彼此电连接的布线图案。 电路通过通孔电连接到布线图案。

公开(公告)号：US07301230B2

公开(公告)日：2007-11-27

申请号：US11020226

申请日：2004-12-27

申请人： Masateru Koide

发明人： Masateru Koide

IPC分类号： H01L23/12 ,  H05K1/18

CPC分类号： H01L23/50 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/01025 ,  H01L2924/01078 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/19106 ,  H05K1/183 ,  H05K3/0035 ,  H05K3/0044 ,  H05K3/381 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/09127 ,  H05K2201/09472 ,  H05K2201/10636 ,  H05K2203/0228 ,  Y02P70/611

摘要： A laminating step includes a second step of laminating a second insulation layer on a conductive pattern last formed at a first step, roughening the surface of the laminated second insulation layer excluding a desired area, and forming a conductive layer on at least the desired area of the surface of the second insulation layer, and a processing step includes a removing step of removing an upper part of the area higher than the second insulation layer on the substrate obtained at the laminating step, and an exposing step of exposing a part of the area of a conductive pattern adjacent to the lower side of the second insulation layer.

摘要翻译： 层压步骤包括第二步骤，将第二绝缘层层压在最后形成的第一步骤的导电图案上，使层压的第二绝缘层的表面粗糙化，除去期望的区域，并且在至少所需的区域上形成导电层 第二绝缘层的表面和加工步骤包括去除在层压步骤获得的基板上高于第二绝缘层的区域的上部的去除步骤，以及暴露步骤， 的导电图案与第二绝缘层的下侧相邻。

公开(公告)号：US20070262427A1

公开(公告)日：2007-11-15

申请号：US11781330

申请日：2007-07-23

申请人： Masateru KOIDE

发明人： Masateru KOIDE

IPC分类号： H01L23/495

CPC分类号： H01L23/04 ,  H01L23/3675 ,  H01L23/552 ,  H01L23/562 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/1616 ,  H01L2924/16251 ,  H01L2924/1659 ,  H01L2924/3025 ,  H01L2224/05599

摘要： A semiconductor device includes a semiconductor element; a board where the semiconductor element is mounted; a heat radiation member thermally connected to the semiconductor element and fixed to the board; and a plurality of outside connection terminals provided on a surface opposite to a surface where the heat radiation member is provided of the board; wherein a fixing position where the heat radiation member is fixed to the board is substantially positioned on an inscribing circle; and the center of the inscribing circle is a center position of the board and the inscribing circle inscribes the heat radiation member.

摘要翻译： 半导体器件包括半导体元件; 安装半导体元件的板; 热连接到所述半导体元件并固定到所述板上的散热构件; 以及多个外部连接端子，设置在与所述板的所述散热构件的表面相反的表面上; 其中所述散热构件固定到所述板的固定位置基本上位于刻印圆上; 并且刻印圆的中心是板的中心位置，并且刻印圆内嵌有散热构件。

公开(公告)号：US20060063303A1

公开(公告)日：2006-03-23

申请号：US11265107

申请日：2005-11-03

申请人： Masateru Koide ,  Misao Umematsu ,  Takashi Kanda ,  Yasuhiro Usui ,  Kenji Fukuzono

发明人： Masateru Koide ,  Misao Umematsu ,  Takashi Kanda ,  Yasuhiro Usui ,  Kenji Fukuzono

IPC分类号： H01L21/50 ,  H01L21/48

CPC分类号： H01L23/642 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/4006 ,  H01L23/49833 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/19106 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/141 ,  H05K1/182 ,  H05K3/3436 ,  H05K2201/049 ,  H05K2201/09072 ,  H05K2201/1053 ,  H05K2201/10734 ,  H05K2201/10977 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/0401

摘要： A packaging method, a packaging structure and a package is substrate capable of restraining a warp of a thin film substrate, increasing a product yield, and building up a sufficient cooling capacity in the case of mounting an LSI having a high exothermic quantity. A package substrate 1 of the invention is such that an opening 11 is formed in a first substrate 12, a thin film substrate (a second substrate) 13 is laminated on the first substrate 12, the opening 11 is covered with the thin film substrate 13. Next, a capacitor (a first electronic part) 14 is inserted into the opening 11 and bonded to the thin film substrate, a resin 15 fills an interior of the opening 11 to a fixed or larger thickness and is hardened, the thin film substrate 13 and the capacitor 14 are thereby sustained by the resin 15, an LSI 16 (a second electronic part) that should be connected to the capacitor 14 is bonded to a surface, on an exposed side, of the thin film substrate 13, and the capacitor 14 is connected to the LSI 16.

摘要翻译： 包装方法，包装结构和包装是能够抑制薄膜基板翘曲的基板，提高产品收率，并且在安装具有高放热量的LSI的情况下建立足够的冷却能力的基板。 本发明的封装基板1使得在第一基板12中形成开口11，在第一基板12上层叠薄膜基板（第二基板）13，开口11被薄膜基板13覆盖 。 接下来，将电容器（第一电子部件）14插入到开口11中并且结合到薄膜基板上，树脂15将开口11的内部填充到固定或更大的厚度并被硬化，薄膜基板13 并且电容器14由树脂15维持，应该连接到电容器14的LSI 16（第二电子部件）被接合到薄膜基板13的暴露侧的表面上，并且电容器 14连接到LSI 16。

公开(公告)号：US20050146017A1

公开(公告)日：2005-07-07

申请号：US10986151

申请日：2004-11-12

申请人： Masateru Koide

发明人： Masateru Koide

IPC分类号： H01L23/32 ,  H01L23/367 ,  H01L23/50 ,  H01L23/538 ,  H01L25/16 ,  H05K1/02 ,  H01L23/15

CPC分类号： H05K1/0263 ,  H01L23/32 ,  H01L23/367 ,  H01L23/50 ,  H01L23/5385 ,  H01L25/162 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K2201/10189 ,  H05K2201/1053 ,  H05K2201/10734 ,  H01L2224/0401

摘要： A package substrate has a power supply path different from a signal supply path to a semiconductor element. A semiconductor element is mounted on a first surface of the package substrate. A second surface opposite to the first surface is provided with external connection terminals. A power supply layer is formed inside the package substrate. The package substrate has electrode terminals provided in a part other than the second surface. The electrode terminals are connected to the power supply layer.

摘要翻译： 封装衬底具有不同于到半导体元件的信号提供路径的电源路径。 半导体元件安装在封装基板的第一表面上。 与第一表面相对的第二表面设置有外部连接端子。 电源层形成在封装衬底的内部。 封装基板具有设置在第二表面以外的部分的电极端子。 电极端子连接到电源层。