公开(公告)号：US20080116558A1

公开(公告)日：2008-05-22

申请号：US11935953

申请日：2007-11-06

申请人： Sun-Won KANG ,  Seung-Duk BAEK

发明人： Sun-Won KANG ,  Seung-Duk BAEK

IPC分类号： H01L23/02 ,  H01G4/06 ,  H01L21/02

CPC分类号： H01G4/06 ,  H01G4/1227 ,  H01G4/308 ,  H01L23/50 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

摘要： A decoupling capacitor, a wafer stack package including the decoupling capacitor, and a method of fabricating the wafer stack package are provided. The decoupling capacitor may include a first electrode formed on an upper surface of a first wafer, a second electrode formed on a lower surface of a second wafer, and an adhesive material having a high dielectric constant and combining the first wafer with the second wafer. In the decoupling capacitor the first and second electrodes operate as two electrodes of the decoupling capacitor, and the adhesive material operates as a dielectric of the decoupling capacitor.

摘要翻译： 提供去耦电容器，包括去耦电容器的晶片堆叠封装以及制造晶片堆叠封装的方法。 去耦电容器可以包括形成在第一晶片的上表面上的第一电极，形成在第二晶片的下表面上的第二电极和具有高介电常数并且将第一晶片与第二晶片组合的粘合材料。 在去耦电容器中，第一和第二电极作为去耦电容器的两个电极工作，并且粘合材料作为去耦电容器的电介质。

公开(公告)号：US20070007663A1

公开(公告)日：2007-01-11

申请号：US11371291

申请日：2006-03-07

申请人： Seung-Duk Baek ,  Sun-Won Kang

发明人： Seung-Duk Baek ,  Sun-Won Kang

IPC分类号： H01L23/48

CPC分类号： H01L23/3114 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/32 ,  H01L24/48 ,  H01L24/50 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/86 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/838 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An embodiment includes a dual interconnection form in which power/ground pads and signal pads of a semiconductor chip are electrically connected to a package substrate in different connection manners. First connection members that electrically connect the power/ground pads with the substrate have relatively large cross-sectional dimensions in comparison to its length, for example, solder bumps or gold bumps. Second connection members that electrically connect the signal pads with the substrate have relatively small cross-sectional dimensions in comparison its length, for example, conductive wires or beam leads. Such different ways of electrically connecting different kinds of pads with the substrate realize the most suitable electrical performance, effectively meeting the needs of high speed and low power consumption of the semiconductor devices.

摘要翻译： 一个实施例包括双重互连形式，其中半导体芯片的电源/接地焊盘和信号焊盘以不同的连接方式电连接到封装基板。 将电源/接地焊盘与基板电连接的第一连接构件与其长度（例如，焊料凸块或金凸块）相比具有相对较大的横截面尺寸。 将信号焊盘与衬底电连接的第二连接构件与其长度（例如，导线或束引线）相比具有相对小的横截面尺寸。 将不同类型的焊盘与衬底电连接的这种不同的方式实现了最适合的电气性能，有效地满足了半导体器件的高速度和低功耗的需要。

公开(公告)号：US07129571B2

公开(公告)日：2006-10-31

申请号：US10977533

申请日：2004-10-28

申请人： Sun-Won Kang

发明人： Sun-Won Kang

IPC分类号： H01L23/02

CPC分类号： H01L23/50 ,  H01L23/13 ,  H01L23/24 ,  H01L23/49838 ,  H01L23/5383 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/06136 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30107 ,  Y10S257/924 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor chip package has a substrate that includes circuit lines provided on first and/or second surfaces, a power plane provided on the second surface, bump lands provided on the second surface and coupled to the circuit lines, and ball lands provided on the first surface. The package further has a semiconductor chip attached to the second surface of the substrate and electrically coupled to the circuit lines, and a dielectric layer provided on the second surface of the substrate. The dielectric layer surrounds laterally the chip, covers the power plane, and exposes the bump lands. The package further has a ground plane provided on both the chip and the dielectric layer, vertical connection bumps provided within the dielectric layer and on the bump lands and electrically coupled to the ground plane, and solder balls provided on the ball lands.

摘要翻译： 半导体芯片封装具有包括设置在第一和/或第二表面上的电路线的基板，设置在第二表面上的电源平面，设置在第二表面上并连接到电路线的凸起焊盘，以及设置在第一表面上的第一 表面。 封装还具有附接到衬底的第二表面并电耦合到电路线的半导体芯片，以及设置在衬底的第二表面上的电介质层。 电介质层横向包围芯片，覆盖电源平面，露出凸起焊盘。 封装还具有设置在芯片和电介质层两者上的接地平面，设置在电介质层内并且在凸起焊盘上并电耦合到接地平面的垂直连接凸块以及设置在球台上的焊球。

公开(公告)号：US20060134833A1

公开(公告)日：2006-06-22

申请号：US11289665

申请日：2005-11-28

申请人： Seung-Duk Baek ,  Sun-Won Kang ,  Sang-Wook Park ,  Dong-Ho Lee ,  Jong-Joo Lee

发明人： Seung-Duk Baek ,  Sun-Won Kang ,  Sang-Wook Park ,  Dong-Ho Lee ,  Jong-Joo Lee

IPC分类号： H01L21/48

CPC分类号： H01L23/49833 ,  H01L23/3128 ,  H01L24/48 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Aspects of the subject matter described herein relate to a packaged semiconductor die which becomes a component of a finished multi-chip package. The packaged semiconductor die comprises a die substrate, a semiconductor package, and a sealant. The die substrate includes an insulating substrate and a circuit pattern formed on the insulating substrate. The semiconductor package has a semiconductor chip electrically coupled to the circuit pattern that is a known good package and is coupled to the die substrate. The sealant seals the semiconductor package. The packaged semiconductor die utilizes a known good package which has passed a series of package tests.

公开(公告)号：US06779303B2

公开(公告)日：2004-08-24

申请号：US10253845

申请日：2002-09-24

申请人： Sang-Ryeol Park ,  Sun-Won Kang ,  Won-Suk Chun

发明人： Sang-Ryeol Park ,  Sun-Won Kang ,  Won-Suk Chun

IPC分类号： E05F1502

CPC分类号： E05F15/443 ,  E05Y2900/55

摘要： A vehicular power window safety device by which the state of a foreign object being stuck is recognized only when the foreign object makes contact with a weather strip mounted on the upper portion of a door frame, deforming the weather strip, and preventing an excessive contact between the window glass and run channel from being misjudged as an object being jammed therebetween and thereby enabling to obtain an operational trustworthiness on the power window safety device. The device comprises a motor for generating the driving power for lifting and lowering a window glass; a weather strip mounted on an upper area of a door frame and inherently provided with a sensor of which electric resistance is changed by pressure provided by a foreign object stuck in between the weather strip and the window glass due to the lifting of the window glass; and a controller for controlling the motor in response to signals supplied from the sensor.

摘要翻译： 只有当异物与安装在门框上部的防风条接触时，才能识别异物被卡住的状态的车辆电动车窗安全装置，使防风条变形，并防止过度接触 窗玻璃和运行通道被误判为物体被卡在其间，从而能够在电动车窗安全装置上获得操作可信赖性。 该装置包括用于产生用于提升和降低窗玻璃的驱动力的电动机; 安装在门框的上部区域上的天气条，固有地设置有传感器，由于窗玻璃的提升，粘附在耐候条和窗玻璃之间的异物所施加的压力使电阻发生变化; 以及控制器，用于响应于从传感器提供的信号来控制电动机。

公开(公告)号：US08928154B2

公开(公告)日：2015-01-06

申请号：US13344803

申请日：2012-01-06

申请人： Sun-Won Kang ,  Young-Hee Song ,  Tae-Gyeong Chung ,  Nam-Seog Kim ,  Seung-Duk Baek

发明人： Sun-Won Kang ,  Young-Hee Song ,  Tae-Gyeong Chung ,  Nam-Seog Kim ,  Seung-Duk Baek

IPC分类号： H01L29/40 ,  H01L25/065 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L24/06 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/45099 ,  H01L2924/00

摘要： A semiconductor module may include a circuit substrate with a first die on the circuit substrate and a second die on the first die. The first die may include at least one first data input/output pad on a first peripheral portion of the first die and at least one first control/address pad on a third peripheral portion, the third peripheral portion being separate from the first peripheral portion of the first die. The second die may include at least one second data input/output pad on a second peripheral portion and at least one second control/address pad on a fourth peripheral portion. The second peripheral portion of the second die is not overlapped with the first peripheral portion of the first die in plan view. The fourth peripheral portion of the second die overlaps at least a portion of the third peripheral portion of the first die.

公开(公告)号：US08922012B2

公开(公告)日：2014-12-30

申请号：US12894540

申请日：2010-09-30

申请人： Jin-Woo Park ,  Eun-Chul Ahn ,  Dong-Kil Shin ,  Sun-Won Kang ,  Jong-Ho Lee

发明人： Jin-Woo Park ,  Eun-Chul Ahn ,  Dong-Kil Shin ,  Sun-Won Kang ,  Jong-Ho Lee

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L24/06 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05018 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/06051 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00012

摘要： In an integrated circuit (IC) chip and a flip chip package having the same, no wiring line is provided and the first electrode pad does not make contact with the wiring line in a pad area of the IC chip. Thus, the first bump structure makes contact with the first electrode regardless of the wiring line in the pad area. The second electrode pad makes contact with the wiring line in a pseudo pad area of the IC chip. Thus, the second bump structure in the pseudo pad area makes contact with an upper surface of the second electrode at a contact point(s) spaced apart from the wiring line under the second electrode.

摘要翻译： 在集成电路（IC）芯片和具有其的倒装芯片封装中，不设置布线，并且第一电极焊盘不与IC芯片的焊盘区域中的布线接触。 因此，与焊盘区域中的布线无关，第一凸块结构与第一电极接触。 第二电极焊盘与IC芯片的伪焊盘区域中的布线接触。 因此，伪焊盘区域中的第二凸块结构在与第二电极下方的布线间隔开的接触点处与第二电极的上表面接触。

公开(公告)号：US08519470B2

公开(公告)日：2013-08-27

申请号：US13076605

申请日：2011-03-31

申请人： Sun-won Kang ,  Hwan-sik Lim

发明人： Sun-won Kang ,  Hwan-sik Lim

IPC分类号： H01L29/788

CPC分类号： H01L23/525 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/29 ,  H01L24/30 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/1412 ,  H01L2224/29015 ,  H01L2224/29017 ,  H01L2224/29019 ,  H01L2224/29028 ,  H01L2224/291 ,  H01L2224/30151 ,  H01L2224/32106 ,  H01L2224/32227 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A semiconductor chip includes a redistribution interconnect that is implemented by shorting bumps, and a semiconductor package and a system each including the semiconductor chip. The semiconductor chip includes a semiconductor substrate, a passivation film disposed on the semiconductor substrate, and a plurality of pseudo bumps disposed on the passivation film. Each pseudo bump is directly connected to adjacent pseudo bumps to form at least one redistribution interconnect.

摘要翻译： 半导体芯片包括通过短路凸起实现的再分配互连，以及包括半导体芯片的半导体封装和系统。 半导体芯片包括半导体衬底，设置在半导体衬底上的钝化膜和设置在钝化膜上的多个伪凸点。 每个伪凸块直接连接到相邻的伪凸点以形成至少一个再分布互连。

公开(公告)号：US20130088838A1

公开(公告)日：2013-04-11

申请号：US13567388

申请日：2012-08-06

申请人： JAE JUN LEE ,  Jeong Hyeon Cho ,  Baek Kyu Choi ,  Sun Won Kang ,  Jung Joon Lee

发明人： JAE JUN LEE ,  Jeong Hyeon Cho ,  Baek Kyu Choi ,  Sun Won Kang ,  Jung Joon Lee

IPC分类号： H05K7/00 ,  H01L21/50 ,  H01L23/50

CPC分类号： H01L23/647 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48195 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/1301 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1441 ,  H01L2924/1443 ,  H01L2924/14511 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19015 ,  H01L2924/1902 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A die package includes a substrate, a die mounted on the substrate, and a ZQ resistor disposed in the die package and connected to the substrate and the die. The ZQ resistor may be used to calibrate impedance of the die.

摘要翻译： 模具封装包括基板，安装在基板上的管芯和设置在管芯封装中并连接到基板和管芯的ZQ电阻器。 ZQ电阻可用于校准模具的阻抗。

公开(公告)号：US08254140B2

公开(公告)日：2012-08-28

申请号：US12357693

申请日：2009-01-22

申请人： Kwang-Yong Lee ,  Jong-Gi Lee ,  Sun-Won Kang ,  Ji-Seok Hong

发明人： Kwang-Yong Lee ,  Jong-Gi Lee ,  Sun-Won Kang ,  Ji-Seok Hong

IPC分类号： H05K7/10

CPC分类号： H05K3/3494 ,  H01L21/565 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11334 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81222 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  H05K1/0212 ,  H05K3/3436 ,  H05K3/4007 ,  H05K2203/101 ,  H01L2924/00 ,  H01L2224/05599

摘要： A mounting substrate includes a substrate, a bonding pad and an induction heating pad. The bonding pad is formed on the substrate, and adhered to a solder ball to mount a semiconductor chip on the substrate. The induction heating pad is disposed adjacent to the bonding pad, the induction heating pad being induction heated by an applied alternating magnetic field to reflow the solder ball. The induction heating pad having a diameter greater than a skin depth in response to the frequency of the applied alternating magnetic field is selectively induction heated in response to a low frequency band of the alternating magnetic field. Accordingly, during a reflow process for a solder ball, the semiconductor chip may be mounted on the mounting substrate to complete a semiconductor package without damaging the mounting substrate, to thereby improve the reliability of the completed semiconductor package.

摘要翻译： 安装基板包括基板，接合焊盘和感应加热垫。 接合焊盘形成在基板上，并且粘附到焊球以将半导体芯片安装在基板上。 感应加热垫设置在接合焊盘附近，感应加热垫被施加的交变磁场感应加热以回流焊球。 响应于所施加的交变磁场的频率具有大于皮肤深度的直径的感应加热垫响应于交变磁场的低频带被选择性地感应加热。 因此，在焊球的回流处理中，可以将半导体芯片安装在安装基板上以完成半导体封装而不损坏安装基板，从而提高完成的半导体封装的可靠性。