公开(公告)号：US20080286494A1

公开(公告)日：2008-11-20

申请号：US12044334

申请日：2008-03-07

申请人： Christos Dimitrios Dimitrakopoulos ,  Stephen McConnell Gates ,  Alfred Grill ,  Michael Wayne Lane ,  Eric Gerhard Liniger ,  Xiao Hu Liu ,  Son Van Nguyen ,  Deborah Ann Neumayer ,  Thomas McCarroll Shaw

发明人： Christos Dimitrios Dimitrakopoulos ,  Stephen McConnell Gates ,  Alfred Grill ,  Michael Wayne Lane ,  Eric Gerhard Liniger ,  Xiao Hu Liu ,  Son Van Nguyen ,  Deborah Ann Neumayer ,  Thomas McCarroll Shaw

IPC分类号： B01J19/08 ,  C23C16/44

CPC分类号： H01L21/76834 ,  C23C16/30 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02348 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  Y10T428/249953 ,  Y10T428/249969 ,  Y10T428/249979

摘要： A method for forming a ultralow dielectric constant layer with controlled biaxial stress is described incorporating the steps of forming a layer containing Si, C, O and H by one of PECVD and spin-on coating and curing the film in an environment containing very low concentrations of oxygen and water each less than 10 ppm. A material is also described by using the method with a dielectric constant of not more than 2.8. The invention overcomes the problem of forming films with low biaxial stress less than 46 MPa.

公开(公告)号：US20080224118A1

公开(公告)日：2008-09-18

申请号：US12127994

申请日：2008-05-28

申请人： James P. Doyle ,  Bruce G. Elmegreen ,  Lia Krusin-Elbaum ,  Chung Hon Lam ,  Xiao Hu Liu ,  Dennis M. Newns ,  Christy S. Tyberg

发明人： James P. Doyle ,  Bruce G. Elmegreen ,  Lia Krusin-Elbaum ,  Chung Hon Lam ,  Xiao Hu Liu ,  Dennis M. Newns ,  Christy S. Tyberg

IPC分类号： H01L47/00

CPC分类号： H01L45/1233 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1286 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1666

摘要： An electrically re-programmable fuse (eFUSE) device for use in integrated circuit devices includes an elongated heater element, an electrically insulating liner surrounding an outer surface of the elongated heater element, corresponding to a longitudinal axis thereof, leaving opposing ends of the elongated heater element in electrical contact with first and second heater electrodes. A phase change material (PCM) surrounds a portion of an outer surface of the electrically insulating liner, a thermally and electrically insulating layer surrounds an outer surface of the PCM, with first and second fuse electrodes in electrical contact with opposing ends of the PCM. The PCM is encapsulated within the electrically insulating liner, the thermally and electrically insulating layer, and the first and second fuse electrodes.

公开(公告)号：US07417315B2

公开(公告)日：2008-08-26

申请号：US10310532

申请日：2002-12-05

申请人： Gareth Geoffrey Hougham ,  S. Jay Chey ,  James Patrick Doyle ,  Xiao Hu Liu ,  Christopher V. Jahnes ,  Paul Alfred Lauro ,  Nancy C. LaBianca ,  Michael J. Rooks

发明人： Gareth Geoffrey Hougham ,  S. Jay Chey ,  James Patrick Doyle ,  Xiao Hu Liu ,  Christopher V. Jahnes ,  Paul Alfred Lauro ,  Nancy C. LaBianca ,  Michael J. Rooks

IPC分类号： H01L21/302 ,  B32B5/22 ,  G02B26/00

CPC分类号： B81B3/0035 ,  H01L2924/0002 ,  Y10T428/249986 ,  H01L2924/00

摘要： A Negative Thermal Expansion system (NTEs) device for TCE compensation or CTE compensation in elastomer composites and conductive elastomer interconnects in microelectronic packaging. One aspect of the present invention provides a method for fabricating micromachine devices that have negative thermal expansion coefficients that can be made into a composite for manipulation of the TCE of the material. These devices and composites made with these devices are in the categories of materials called “smart materials” or “responsive materials.” Another aspect of the present invention provides microdevices comprised of dual opposed bilayers of material where the two bilayers are attached to one another at the peripheral edges only, and where the bilayers themselves are at a minimum stress conditions at a reference temperature defined by the temperature at which the bilayers are formed. These devices have the technologically useful property of volumetrically expanding upon lowering of the device temperature below the reference or processing temperature.

摘要翻译： 用于微电子封装中弹性体复合材料和导电弹性体互连的TCE补偿或CTE补偿的负热膨胀系统（NTE）装置。 本发明的一个方面提供了一种用于制造具有负热膨胀系数的微机械装置的方法，该热膨胀系数可以制成用于操纵材料的TCE的复合材料。 这些设备和这些设备制成的复合材料属于称为“智能材料”或“响应材料”的材料类别。 本发明的另一方面提供了由双重相对的双层材料构成的微器件，其中两个双层仅在外围边缘处彼此附接，并且其中双层本身处于由温度定义的参考温度下的最小应力条件 双层形成。 当器件温度降低到参考温度或加工温度以下时，这些器件具有技术上有用的特性。

公开(公告)号：US20080173985A1

公开(公告)日：2008-07-24

申请号：US11626552

申请日：2007-01-24

申请人： Michael P. Belyansky ,  Griselda Bonilla ,  Xiao Hu Liu ,  Son Van Nguyen ,  Thomas M. Shaw ,  Hosadurga K. Shobha ,  Daewon Yang

发明人： Michael P. Belyansky ,  Griselda Bonilla ,  Xiao Hu Liu ,  Son Van Nguyen ,  Thomas M. Shaw ,  Hosadurga K. Shobha ,  Daewon Yang

IPC分类号： H01L23/58 ,  H01L21/318

CPC分类号： H01L21/02123 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/318 ,  H01L21/3185 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76834

摘要： A dielectric cap and related methods are disclosed. In one embodiment, the dielectric cap includes a dielectric material having an optical band gap (e.g. greater than about 3.0 electron-Volts) to substantially block ultraviolet radiation during a curing treatment, and including nitrogen with electron donor, double bond electrons. The dielectric cap exhibits a high modulus and is stable under post ULK UV curing treatments for, for example: copper low k back-end-of-line (BEOL) nanoelectronic devices, leading to less film and device cracking and improved reliability,

摘要翻译： 公开了介电盖和相关方法。 在一个实施例中，电介质盖包括具有光学带隙（例如大于约3.0电子伏特）的电介质材料，以在固化处理期间基本上阻挡紫外线辐射，并且包括氮与电子给体，双键电子。 电介质盖表现出高模量，并且在ULK UV固化处理后稳定，例如：铜低k后端（BEOL）纳米电子器件，导致更少的膜和器件开裂和改善的可靠性，

公开(公告)号：US06972209B2

公开(公告)日：2005-12-06

申请号：US10306534

申请日：2002-11-27

申请人： Birendra N. Agarwala ,  Conrad A. Barile ,  Hormazdyar M. Dalal ,  Brett H. Engle ,  Michael Lane ,  Ernest Levine ,  Xiao Hu Liu ,  Vincent McGahay ,  John F. McGrath ,  Conal E. Murray ,  Jawahar P. Nayak ,  Du B. Nguyen ,  Hazara S. Rathore ,  Thomas M. Shaw

发明人： Birendra N. Agarwala ,  Conrad A. Barile ,  Hormazdyar M. Dalal ,  Brett H. Engle ,  Michael Lane ,  Ernest Levine ,  Xiao Hu Liu ,  Vincent McGahay ,  John F. McGrath ,  Conal E. Murray ,  Jawahar P. Nayak ,  Du B. Nguyen ,  Hazara S. Rathore ,  Thomas M. Shaw

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/00

CPC分类号： H01L23/53295 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76838 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10T428/24917 ,  H01L2924/00

摘要： A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material. The dielectric layer of each of the multiple interconnection levels includes a soft low-k dielectric material, wherein the cantilever and set of stacked via-studs are integrated within the soft low-k dielectric material to increase resistance to thermal fatigue crack formation. In one embodiment, each of the set of stacked via-studs in the low-k dielectric material layers is provided with a cantilever, such that the cantilevers are interwoven by connecting a cantilever on one level to a bulk portion of the conductor line on adjacent levels of interconnection, thereby increasing flexibility of stacked via-studs between interconnection levels.

摘要翻译： 一种多级半导体集成电路（IC）结构，包括在半导体衬底上包括电介质材料层的第一互连电平，所述介电材料层包括用于钝化半导体器件的致密材料和其下的局部互连; 形成在致密电介质材料层之上的电介质材料的多个互连层，每层介电材料包括至少一层低k电介质材料; 以及在低k电介质材料层中的一组堆叠的通孔螺钉，每组所述一组堆叠通孔柱互连一个或多个图案化导电结构，包括形成在低k电介质材料中的悬臂的导电结构。 多个互连级别中的每一个的电介质层包括软的低k电介质材料，其中悬臂和一组堆叠的通孔螺钉集成在软低k电介质材料内，以增加对热疲劳裂纹形成的抵抗力。 在一个实施例中，低k电介质材料层中的每组叠置通孔螺柱设置有悬臂，使得悬臂通过将一个级上的悬臂连接到相邻的导体线的主体部分而交织 互连级别，从而增加互连级别之间堆叠通孔的灵活性。

公开(公告)号：US08796133B2

公开(公告)日：2014-08-05

申请号：US13553941

申请日：2012-07-20

申请人： Griselda Bonilla ,  Timothy H. Daubenspeck ,  Mark C. H. Lamorey ,  Howard S. Landis ,  Xiao Hu Liu ,  David L. Questad ,  Thomas M. Shaw ,  David B. Stone

发明人： Griselda Bonilla ,  Timothy H. Daubenspeck ,  Mark C. H. Lamorey ,  Howard S. Landis ,  Xiao Hu Liu ,  David L. Questad ,  Thomas M. Shaw ,  David B. Stone

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L23/53295 ,  H01L23/3192 ,  H01L23/522 ,  H01L23/5329 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13021 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2224/05552

摘要： A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads.

摘要翻译： 一种在受控的崩溃芯片连接（C4）下减少白色凸块形成和电介质裂纹的方法。 该方法包括制造具有多个金属化层的衬底，一个或多个层是低k电介质材料。 衬底包括用于C4的多个附接垫。 该制造包括在位于至少一些附接垫下方的衬底的部分中，选择性地形成具有比任何一种或多种低k电介质材料中的任何一种具有更高杨氏弹性模量的金属填充物的衬底的至少一部分。

公开(公告)号：US08679943B2

公开(公告)日：2014-03-25

申请号：US13215738

申请日：2011-08-23

申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Xiao Hu Liu ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Xiao Hu Liu ,  Devendra K. Sadana

IPC分类号： H01L21/30

CPC分类号： H01L21/30 ,  H01L31/1892 ,  Y02E10/50

摘要： A spalling method is provided that includes depositing a stressor layer on surface of a base substrate, and contacting the stressor layer with a planar transfer. The planar transfer surface is then traversed along a plane that is parallel to and having a vertical offset from the upper surface of the base substrate. The planar transfer surface is traversed in a direction from a first edge of the base substrate to an opposing second edge of the base substrate to cleave the base substrate and transfer a spalled portion of the base substrate to the planar transfer surface. The vertical offset between the plane along which the planar transfer surface is traversed and the upper surface of the base substrate is a fixed distance. The fixed distance of the vertical offset provides a uniform spalling force. A spalling method is also provided that includes a transfer roller.

摘要翻译： 提供了一种剥落方法，其包括在基底表面上沉积应力层，并使应力层与平面转移接触。 然后，平面转移表面沿着平行于并且具有从基底基板的上表面垂直偏移的平面穿过。 平面转移表面在从基底基板的第一边缘到基底基板的相对的第二边缘的方向上穿过，以将基底基板切割并将基底基板的剥离部分转印到平面转印表面。 平面转移面沿着平面移动的平面与基底基板的上表面之间的垂直偏移是固定的距离。 垂直偏移的固定距离提供均匀的剥落力。 还提供了包括转印辊的剥落方法。

公开(公告)号：US20140021622A1

公开(公告)日：2014-01-23

申请号：US13553941

申请日：2012-07-20

申请人： Griselda Bonilla ,  Timothy H. Daubenspeck ,  Mark C.H. Lamorey ,  Howard S. Landis ,  Xiao Hu Liu ,  David L. Questad ,  Thomas M. Shaw ,  David B. Stone

发明人： Griselda Bonilla ,  Timothy H. Daubenspeck ,  Mark C.H. Lamorey ,  Howard S. Landis ,  Xiao Hu Liu ,  David L. Questad ,  Thomas M. Shaw ,  David B. Stone

IPC分类号： H01L23/52 ,  H01L21/60

CPC分类号： H01L23/53295 ,  H01L23/3192 ,  H01L23/522 ,  H01L23/5329 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13021 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2224/05552

摘要： A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads.

摘要翻译： 一种在受控的崩溃芯片连接（C4）下减少白色凸块形成和电介质裂纹的方法。 该方法包括制造具有多个金属化层的衬底，一个或多个层是低k电介质材料。 衬底包括用于C4的多个附接垫。 该制造包括在位于至少一些附接垫下方的衬底的部分中，选择性地形成具有比任何一种或多种低k电介质材料中的任何一种具有更高杨氏弹性模量的金属填充物的衬底的至少一部分。

公开(公告)号：US20130052798A1

公开(公告)日：2013-02-28

申请号：US13215738

申请日：2011-08-23

申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Xiao Hu Liu ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Xiao Hu Liu ,  Devendra K. Sadana

IPC分类号： H01L21/30

CPC分类号： H01L21/30 ,  H01L31/1892 ,  Y02E10/50

摘要： A spalling method is provided that includes depositing a stressor layer on surface of a base substrate, and contacting the stressor layer with a planar transfer. The planar transfer surface is then traversed along a plane that is parallel to and having a vertical offset from the upper surface of the base substrate. The planar transfer surface is traversed in a direction from a first edge of the base substrate to an opposing second edge of the base substrate to cleave the base substrate and transfer a spalled portion of the base substrate to the planar transfer surface. The vertical offset between the plane along which the planar transfer surface is traversed and the upper surface of the base substrate is a fixed distance. The fixed distance of the vertical offset provides a uniform spalling force. A spalling method is also provided that includes a transfer roller.

摘要翻译： 提供了一种剥落方法，其包括在基底表面上沉积应力层，并使应力层与平面转移接触。 然后，平面转移表面沿着平行于并且具有从基底基板的上表面垂直偏移的平面穿过。 平面转移表面在从基底基板的第一边缘到基底基板的相对的第二边缘的方向上穿过，以将基底基板切割并将基底基板的剥离部分转印到平面转印表面。 平面转移面沿着平面移动的平面与基底基板的上表面之间的垂直偏移是固定的距离。 垂直偏移的固定距离提供均匀的剥落力。 还提供了包括转印辊的剥落方法。

公开(公告)号：US20120270353A1

公开(公告)日：2012-10-25

申请号：US13532991

申请日：2012-06-26

申请人： Bruce G. Elmegreen ,  Lia Krusin-Elbaum ,  Glenn J. Martyna ,  Xiao Hu Liu ,  Dennis M. Newns ,  Kuan-Neng Chen

发明人： Bruce G. Elmegreen ,  Lia Krusin-Elbaum ,  Glenn J. Martyna ,  Xiao Hu Liu ,  Dennis M. Newns ,  Kuan-Neng Chen

IPC分类号： H01L21/02

CPC分类号： H01L49/00 ,  H01C10/103

摘要： A coupling structure for coupling piezoelectric material generated stresses to an actuated device of an integrated circuit includes a rigid stiffener structure formed around a piezoelectric (PE) material and the actuated device, the actuated device comprising a piezoresistive (PR) material that has an electrical resistance dependent upon an applied pressure thereto; and a soft buffer structure formed around the PE material and PR material, the buffer structure disposed between the PE and PR materials and the stiffener structure, wherein the stiffener structure clamps both the PE and PR materials to a substrate over which the PE and PR materials are formed, and wherein the soft buffer structure permits the PE material freedom to move relative to the PR material, thereby coupling stress generated by an applied voltage to the PE material to the PR material so as change the electrical resistance of the PR material.

摘要翻译： 用于将压电材料产生的应力耦合到集成电路的致动装置的耦合结构包括围绕压电（PE）材料形成的刚性加强结构和致动装置，该致动装置包括具有电阻的压阻（PR）材料 取决于施加的压力; 以及围绕PE材料和PR材料形成的软缓冲结构，缓冲结构设置在PE和PR材料之间以及加强件结构之间，其中加强件结构将PE和PR材料夹持到基底上，PE和PR材料 并且其中软缓冲结构允许PE材料相对于PR材料自由移动，从而将由施加的电压产生的应力耦合到PE材料到PR材料，从而改变PR材料的电阻。