公开(公告)号：US10818805B2

公开(公告)日：2020-10-27

申请号：US16185837

申请日：2018-11-09

Applicant: Infineon Technologies AG

Inventor： Franz-Peter Kalz ,  Jochen Dangelmaier

IPC: H01L31/0216 ,  H01L31/18 ,  B81B7/02 ,  B81C1/00 ,  B81B7/00 ,  H01L31/0203 ,  H01L31/0232

Abstract: A semiconductor sensor device includes a substrate including a first main face and a second main face opposite the first main face, a semiconductor element including a sensing region, the semiconductor element on the first main face of the substrate and being electrically coupled to the substrate, a lid on the first main face of the substrate and forming a cavity, wherein the semiconductor element is in the cavity, and a vapor deposited dielectric coating covering the semiconductor element and the first main face of the substrate, the vapor deposited dielectric coating having an opening over the sensing region, wherein the second main face of the substrate is at least partially free of the vapor deposited dielectric layer.

公开(公告)号：US20180294210A1

公开(公告)日：2018-10-11

申请号：US15949533

申请日：2018-04-10

Applicant: Infineon Technologies AG

Inventor： Manfred Schindler ,  Franz-Peter Kalz ,  Volker Strutz

IPC: H01L23/495 ,  H01L23/31 ,  H01L25/16 ,  H01L21/48 ,  H01L23/00 ,  H01L23/492 ,  H01L43/04

CPC classification number: H01L23/49586 ,  H01L21/4825 ,  H01L23/3121 ,  H01L23/4924 ,  H01L23/49517 ,  H01L23/49541 ,  H01L23/49582 ,  H01L23/49589 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L25/16 ,  H01L43/04 ,  H01L2224/13101 ,  H01L2224/16245 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A package and method of making a package. In one example, the package includes an at least partially electrically conductive carrier, a passive component mounted on the carrier, and an at least partially electrically conductive connection structure electrically connecting the carrier with the component and comprising spacer particles configured for spacing the carrier with regard to the component.

公开(公告)号：US20170352638A1

公开(公告)日：2017-12-07

申请号：US15682747

申请日：2017-08-22

Applicant: Infineon Technologies AG

Inventor： Volker Strutz ,  Rainer Markus Schaller ,  Franz-Peter Kalz

IPC: H01L23/00 ,  H01L27/22

CPC classification number: H01L24/29 ,  G01R33/0052 ,  H01L23/49503 ,  H01L23/49506 ,  H01L23/4951 ,  H01L23/49513 ,  H01L23/49548 ,  H01L23/60 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L27/22 ,  H01L2224/2929 ,  H01L2224/29393 ,  H01L2224/29499 ,  H01L2224/29561 ,  H01L2224/2957 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/85986 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/30101 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate, a semiconductor die, and an antistatic die attach material between the substrate and the semiconductor die. The antistatic die attach material includes a mixture of a nonconductive adhesive material and carbon black or graphite. In one example, the antistatic die attach material has a resistivity between 101 Ω·cm and 1010 Ω·cm.

公开(公告)号：US09159701B2

公开(公告)日：2015-10-13

申请号：US14028577

申请日：2013-09-17

Applicant: Infineon Technologies AG

Inventor： Khalil Hosseini ,  Joachim Mahler ,  Franz-Peter Kalz ,  Joachim Voelter ,  Ralf Wombacher

IPC: H01L23/52 ,  H01L21/60 ,  H01L23/48 ,  H01L21/50 ,  H01L21/56 ,  H01L23/00 ,  H01L23/495 ,  H01L23/492 ,  H01L23/498

CPC classification number: H01L25/0655 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/492 ,  H01L23/49558 ,  H01L23/49575 ,  H01L23/49586 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83095 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/8382 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2224/83

Abstract: A method of manufacturing a chip package is provided. The method may include electrically contacting at least one first chip, the first chip including a first side and a second side opposite the first side, with its second side to an electrically conductive carrier. An insulating layer is formed over at least a part of the electrically conductive carrier and over at least a part of the first side of the chip. At least one second chip is arranged over the insulating layer. An encapsulating material is formed over the first chip and the second chip. Electrical contacts are formed through the encapsulation material to at least one contact of the at least one first chip and to at least one contact of the at least one second chip.

Abstract translation: 提供了一种制造芯片封装的方法。 该方法可以包括电接触至少一个第一芯片，第一芯片包括第一侧和与第一侧相对的第二侧，其第二侧为导电载体。 绝缘层形成在导电载体的至少一部分上并且在芯片的第一侧的至少一部分上方。 至少一个第二芯片布置在绝缘层上。 在第一芯片和第二芯片上形成封装材料。 电触头通过封装材料形成至少一个第一芯片和至少一个第二芯片的至少一个触点的至少一个触点。

公开(公告)号：US20150111343A1

公开(公告)日：2015-04-23

申请号：US14581653

申请日：2014-12-23

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Manfred Mengel ,  Khalil Hosseini ,  Klaus Schmidt ,  Franz-Peter Kalz

IPC: H01L23/00

CPC classification number: H01L24/83 ,  H01L24/00 ,  H01L24/24 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L2224/04026 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2224/245 ,  H01L2224/2499 ,  H01L2224/26165 ,  H01L2224/27462 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32245 ,  H01L2224/73217 ,  H01L2224/82002 ,  H01L2224/82101 ,  H01L2224/82345 ,  H01L2224/82385 ,  H01L2224/82986 ,  H01L2224/831 ,  H01L2224/83851 ,  H01L2224/92144 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01028 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01047

Abstract: An electronic component includes an electrically conductive carrier. The electrically conductive carrier includes a carrier surface and a semiconductor chip includes a chip surface. One or both of the carrier surface and the chip surface include a non-planar structure. The chip is attached to the carrier with the chip surface facing towards the carrier surface so that a gap is provided between the chip surface and the carrier surface due to the non-planar structure of one or both of the carrier surface and the first chip surface. The electronic component further includes a first galvanically deposited metallic layer situated in the gap.

Abstract translation: 电子部件包括导电载体。 导电载体包括载体表面，半导体芯片包括芯片表面。 载体表面和芯片表面中的一个或两个包括非平面结构。 芯片附着到载体上，其芯片表面面向载体表面，使得由于载体表面和第一芯片表面之一或两者的非平面结构，在芯片表面和载体表面之间提供间隙 。 电子部件还包括位于间隙中的第一电沉积金属层。

公开(公告)号：US20150076672A1

公开(公告)日：2015-03-19

申请号：US14028577

申请日：2013-09-17

Applicant: Infineon Technologies AG

Inventor： Khalil Hosseini ,  Joachim Mahler ,  Franz-Peter Kalz ,  Joachim Voelter ,  Ralf Wombacher

IPC: H01L23/00 ,  H01L23/495

CPC classification number: H01L25/0655 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/492 ,  H01L23/49558 ,  H01L23/49575 ,  H01L23/49586 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83095 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/8382 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2224/83

Abstract: A method of manufacturing a chip package is provided. The method may include electrically contacting at least one first chip, the first chip including a first side and a second side opposite the first side, with its second side to an electrically conductive carrier. An insulating layer is formed over at least a part of the electrically conductive carrier and over at least a part of the first side of the chip. At least one second chip is arranged over the insulating layer. An encapsulating material is formed over the first chip and the second chip. Electrical contacts are formed through the encapsulation material to at least one contact of the at least one first chip and to at least one contact of the at least one second chip.

Abstract translation: 提供了一种制造芯片封装的方法。 该方法可以包括电接触至少一个第一芯片，第一芯片包括第一侧和与第一侧相对的第二侧，其第二侧为导电载体。 绝缘层形成在导电载体的至少一部分上并且在芯片的第一侧的至少一部分上方。 至少一个第二芯片布置在绝缘层上。 在第一芯片和第二芯片上形成封装材料。 电触头通过封装材料形成至少一个第一芯片和至少一个第二芯片的至少一个触点的至少一个触点。

公开(公告)号：US20140197527A1

公开(公告)日：2014-07-17

申请号：US13742455

申请日：2013-01-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Manfred Mengel ,  Joachim Mahler ,  Khalil Hosseini ,  Franz-Peter Kalz

IPC: H01L23/495 ,  H01L21/77

CPC classification number: H01L21/4807 ,  H01L21/4825 ,  H01L21/56 ,  H01L21/77 ,  H01L23/3731 ,  H01L23/3735 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49586 ,  H01L24/27 ,  H01L24/743 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L2924/07802 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A chip arrangement is provided, the chip arrangement, including a carrier; a first chip electrically connected to the carrier; a ceramic layer disposed over the carrier; and a second chip disposed over the ceramic layer; wherein the ceramic layer has a porosity in the range from about 3% to about 70%.

Abstract translation: 提供了芯片布置，芯片布置包括载体; 电连接到所述载体的第一芯片; 布置在所述载体上的陶瓷层; 以及设置在所述陶瓷层上的第二芯片; 其中所述陶瓷层的孔隙率在约3％至约70％的范围内。