公开(公告)号：US20240063127A1

公开(公告)日：2024-02-22

申请号：US17889238

申请日：2022-08-16

Applicant: Intel Corporation

Inventor： Jeremy D. ECTON ,  Brandon C. MARIN ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Suddhasattwa NAD

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/13 ,  H01L23/15 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/13 ,  H01L23/15 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L2924/1511 ,  H01L2924/15153 ,  H01L2924/152 ,  H01L2924/15788 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate with a cavity, where the first substrate comprises glass. In an embodiment, a second substrate is in the cavity. In an embodiment, a bond film covers a bottom of the second substrate and extends up sidewalls of the second substrate.

公开(公告)号：US20230137877A1

公开(公告)日：2023-05-04

申请号：US17517152

申请日：2021-11-02

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Haobo CHEN ,  Omkar KARHADE ,  Malavarayan SANKARASUBRAMANIAN ,  Dingying XU ,  Gang DUAN ,  Bai NIE ,  Xiaoying GUO ,  Kristof DARMAWIKARTA ,  Hongxia FENG ,  Srinivas PIETAMBARAM ,  Jeremy D. ECTON

IPC: H01L23/00 ,  H01L25/065

Abstract: No-remelt solder joints can eliminate die or substrate movement in downstream reflow processes. In one example, one or more solder joints between two substrates can be formed as full IMC (intermetallic compound) solder joints. In one example, a full IMC solder joint includes a continuous layer (e.g., from the top pad to bottom pad) of intermetallic compounds. In one example, a full IMC joint can be formed by dispensing a no-remelt solder paste on some of the pads of one or both substrates to be bonded together.

公开(公告)号：US20230087810A1

公开(公告)日：2023-03-23

申请号：US17482852

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Jeremy D. ECTON ,  Kristof DARMAWIKARTA ,  Suddhasattwa NAD ,  Oscar OJEDA ,  Bai NIE ,  Brandon C. MARIN ,  Gang DUAN ,  Jacob VEHONSKY ,  Onur OZKAN ,  Nicholas S. HAEHN

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a plurality of stacked layers. In an embodiment, a first trace is on a first layer, wherein the first trace has a first thickness. In an embodiment, a second trace is on the first layer, wherein the second trace has a second thickness that is greater than the first thickness. In an embodiment, a second layer is over the first trace and the second trace.

公开(公告)号：US20230027030A1

公开(公告)日：2023-01-26

申请号：US17958296

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Changhua LIU ,  Xiaoying GUO ,  Aleksandar ALEKSOV ,  Steve S. CHO ,  Leonel ARANA ,  Robert MAY ,  Gang DUAN

IPC: H01L23/00

Abstract: A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.

公开(公告)号：US20200006232A1

公开(公告)日：2020-01-02

申请号：US16024707

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Rahul MANEPALLI ,  Gang DUAN

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.

公开(公告)号：US20250144857A1

公开(公告)日：2025-05-08

申请号：US18500132

申请日：2023-11-02

Applicant: Intel Corporation

Inventor： Zhixin XIE ,  Yi LI ,  Jesse JONES ,  Gang DUAN ,  Andrew JIMENEZ ,  Jung Kyu HAN ,  Yekan WANG

IPC: B29C45/14 ,  B29C45/26

Abstract: Various aspects may provide a molding system. The molding system may include a molding unit which includes a first mold panel and a second mold panel. The first mold panel and the second mold panel may include a mold cavity which surrounds a semiconductor workpiece along a side surface of the semiconductor workpiece, with the first mold panel and the second mold panel engaged with the semiconductor workpiece. Various aspects may also provide a molding method which utilize the molding system.

公开(公告)号：US20250112136A1

公开(公告)日：2025-04-03

申请号：US18374937

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Jesse JONES ,  Zhixin XIE ,  Bai NIE ,  Shaojiang CHEN ,  Joshua STACEY ,  Mitchell PAGE ,  Brandon C. MARIN ,  Jeremy D. ECTON ,  Nicholas S. HAEHN ,  Astitva TRIPATHI ,  Yuqin LI ,  Edvin CETEGEN ,  Jason M. GAMBA ,  Jacob VEHONSKY ,  Jianyong MO ,  Makoyi WATSON ,  Shripad GOKHALE ,  Mine KAYA ,  Kartik SRINIVASAN ,  Haobo CHEN ,  Ziyin LIN ,  Kyle ARRINGTON ,  Jose WAIMIN ,  Ryan CARRAZZONE ,  Hongxia FENG ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Gang DUAN ,  Dingying David XU ,  Hiroki TANAKA ,  Ashay DANI ,  Praveen SREERAMAGIRI ,  Yi LI ,  Ibrahim EL KHATIB ,  Aaron GARELICK ,  Robin MCREE ,  Hassan AJAMI ,  Yekan WANG ,  Andrew JIMENEZ ,  Jung Kyu HAN ,  Hanyu SONG ,  Yonggang Yong LI ,  Mahdi MOHAMMADIGHALENI ,  Whitney BRYKS ,  Shuqi LAI ,  Jieying KONG ,  Thomas HEATON ,  Dilan SENEVIRATNE ,  Yiqun BAI ,  Bin MU ,  Mohit GUPTA ,  Xiaoying GUO

IPC: H01L23/498 ,  H01L23/15

Abstract: Embodiments disclosed herein include apparatuses with glass core package substrates. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. A sidewall is between the first surface and the second surface, and the substrate comprises a glass layer. In an embodiment, a via is provided through the substrate between the first surface and the second surface, and the via is electrically conductive. In an embodiment, a layer in contact with the sidewall of the substrate surrounds a perimeter of the substrate.

公开(公告)号：US20240210634A1

公开(公告)日：2024-06-27

申请号：US18089501

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Zhixin XIE ,  Jung Kyu HAN ,  Gang DUAN

IPC: G02B6/42 ,  G02B1/04 ,  G02B3/00

CPC classification number: G02B6/4206 ,  G02B1/041 ,  G02B3/0087 ,  G02B6/4214 ,  G02B6/428

Abstract: Embodiments disclosed herein include a package substrate. In an embodiment, the package substrate comprises a substrate and an optical fiber in the substrate. In an embodiment, a lens is optically coupled to the optical fiber. In an embodiment, the lens is a gradient index (GRIN) lens.

公开(公告)号：US20240186281A1

公开(公告)日：2024-06-06

申请号：US18060617

申请日：2022-12-01

Applicant: Intel Corporation

Inventor： Minglu LIU ,  Andrey GUNAWAN ,  Gang DUAN

IPC: H01L23/00 ,  H01L25/00

CPC classification number: H01L24/75 ,  H01L24/81 ,  H01L24/95 ,  H01L25/50 ,  H01L25/0655

Abstract: The present disclosure is directed to a thermocompression bonding tool having a bond head with a surface for compression and heating and a sensor, a stage for compression and heating, and a controller, and a method for its use for chip gap height and alignment control. For chip gap height and alignment control, the controller is provided with a recipe displacement and temperature profile and measured offsets.

公开(公告)号：US20240186279A1

公开(公告)日：2024-06-06

申请号：US18060577

申请日：2022-12-01

Applicant: Intel Corporation

Inventor： Minglu LIU ,  Yosuke KANAOKA ,  Jung Kyu HAN ,  Gang DUAN ,  Ziyin LIN

IPC: H01L23/00 ,  B32B37/12

CPC classification number: H01L24/75 ,  B32B37/12 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32225 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/7531 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/83874 ,  H01L2924/0635 ,  H01L2924/0665 ,  H01L2924/069 ,  H01L2924/0715

Abstract: The present disclosure relates to a system. The system may include a stage configured to support a substrate. The system may also include a bondhead configured to press a device against the substrate. The system may further include a light source configured to emit UV light towards the stage.