公开(公告)号：US10438930B2

公开(公告)日：2019-10-08

申请号：US15639640

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： Omkar Karhade ,  Christopher L. Rumer ,  Nitin Deshpande ,  Robert M. Nickerson

IPC: H01L23/48 ,  H01L23/52 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/54 ,  H01L23/04 ,  H01L25/10

Abstract: Systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages are provided. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A gap forms between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package. on an organic substrate. A curable fluid material, such as a molding compound, may be flowed both in the interstitial spaces between the PoP semiconductor packages and into the gap between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package.

公开(公告)号：US09820384B2

公开(公告)日：2017-11-14

申请号：US14102676

申请日：2013-12-11

Applicant: Intel Corporation

Inventor： Sasha Oster ,  Robert L. Sankman ,  Charles Gealer ,  Omkar Karhade ,  John S. Guzek ,  Ravi V. Mahajan ,  James C. Matayabas, Jr. ,  Johanna Swan ,  Feras Eid ,  Shawna Liff ,  Timothy McIntosh ,  Telesphor Kamgaing ,  Adel Elsherbini ,  Kemal Aygun

IPC: H05K1/18 ,  H05K13/04 ,  H01L23/00 ,  H05K1/03 ,  G06F1/16 ,  H01L21/56

CPC classification number: H05K1/189 ,  G06F1/163 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H05K1/0393 ,  H05K1/181 ,  H05K1/185 ,  H05K13/0469 ,  H05K2201/0137 ,  H05K2203/1469 ,  Y10T29/49146 ,  H01L2924/00

Abstract: This disclosure relates generally to devices, systems, and methods for making a flexible microelectronic assembly. In an example, a polymer is molded over a microelectronic component, the polymer mold assuming a substantially rigid state following the molding. A routing layer is formed with respect to the microelectronic component and the polymer mold, the routing layer including traces electrically coupled to the microelectronic component. An input is applied to the polymer mold, the polymer mold transitioning from the substantially rigid state to a substantially flexible state upon application of the input.

公开(公告)号：US09583470B2

公开(公告)日：2017-02-28

申请号：US14135209

申请日：2013-12-19

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Nitin Deshpande

IPC: H01L23/488 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/18 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/1131 ,  H01L2224/13011 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13078 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/16056 ,  H01L2224/16059 ,  H01L2224/16155 ,  H01L2224/16238 ,  H01L2224/8109 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81345 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2924/12042 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/3841 ,  H01L2924/00

Abstract: An electronic device including a solder pad structure and methods of forming an electrical interconnection are shown. Solder pads including one or more projections extending from the pads are shown where the projections occupy only a fraction of a surface area of the pads. Processes such as thermal compression bonding using solder pads as described are also shown.

Abstract translation: 示出了包括焊盘结构的电子设备和形成电互连的方法。 示出了包括从焊盘延伸的一个或多个突起的焊盘，其中突起仅占据焊盘表面积的一部分。 还示出了如所描述的使用焊盘的热压接的工艺。

公开(公告)号：US09576942B1

公开(公告)日：2017-02-21

申请号：US14974811

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Nitin Deshpande ,  Bassam M. Ziadeh ,  Yoshihiro Tomita

IPC: H01L23/02 ,  H01L25/18 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/26155 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49109 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/81203 ,  H01L2224/83 ,  H01L2224/83851 ,  H01L2224/85 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06558 ,  H01L2225/06593 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/19104 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2224/45099

Abstract: An integrated circuit assembly that includes a substrate; a member formed on the substrate; a first die mounted to the substrate within an opening in the member such that there is space between the first die and the member and the member surrounds the first die, and wherein the first die does not extend above an upper surface of the member; an underfill between the first the die and the substrate, wherein the underfill at least partially fills the space between the die and member; and a second die mounted to the first die and the member, wherein the second die is mounted to the member on all sides of the opening.

Abstract translation: 一种包括基板的集成电路组件; 形成在基板上的部件; 在所述构件中的开口内安装到所述基板的第一模具，使得在所述第一模具和所述构件之间存在空间，并且所述构件围绕所述第一模具，并且其中所述第一模具不在所述构件的上表面上方延伸; 第一模具和衬底之间的底部填充物，其中底部填充物至少部分地填充模具和构件之间的空间; 以及安装到所述第一模具和所述构件的第二模具，其中所述第二模具安装到所述开口的所有侧面上的所述构件。

公开(公告)号：US20240063147A1

公开(公告)日：2024-02-22

申请号：US17891704

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Mohammad Enamul Kabir ,  Johanna Swan ,  Omkar Karhade ,  Kimin Jun ,  Feras Eid ,  Shawna Liff ,  Xavier Brun ,  Bhaskar Jyoti Krishnatreya ,  Tushar Talukdar ,  Haris Khan Niazi

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/29

CPC classification number: H01L23/564 ,  H01L24/08 ,  H01L24/24 ,  H01L25/0652 ,  H01L24/19 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/291 ,  H01L2224/08145 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/37001 ,  H01L2224/24145 ,  H01L24/73 ,  H01L2224/73259 ,  H01L2224/24225 ,  H01L2224/73209 ,  H01L2224/2499

Abstract: Techniques and mechanisms to mitigate corrosion to via structures of a composite chiplet. In an embodiment, a composite chiplet comprises multiple integrated circuit (IC) components which are each in a different respective one of multiple levels. One or more conductive vias extend through an insulator layer in a first level of the multiple levels. An annular structure of the composite chiplet extends vertically through the insulator layer, and surrounds the one or more conductive vias in the insulator layer. The annular structure mitigates an exposure of the one or more conductive vias to moisture which is in a region of the insulator layer that is not surrounded by the annular structure. In another embodiment, the annular structure further surrounds an IC component which extends in the insulator layer.

公开(公告)号：US20230207545A1

公开(公告)日：2023-06-29

申请号：US17561832

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Omkar Karhade ,  Nitin Deshpande

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L25/18 ,  H01L24/13 ,  H01L23/3185 ,  H01L23/481 ,  H01L2224/13147 ,  H01L2924/014

Abstract: An integrated circuit (IC) package comprises a first IC die comprising a first hardware interface at a first side of the first die, and one or more first conductive contacts at the first side. A second IC die coupled to the first die comprises a second hardware interface at a second side of the second die. Second conductive contacts of the first hardware interface are each in direct contact with a respective one of third conductive contacts of the second hardware interface. A third hardware interface comprises: one or more interconnect structures, each coupled to a respective one of the one or more first conductive contacts and each comprising a fourth conductive contact, and fifth conductive contacts at a third side of the second die, wherein the one or more interconnect structures are each to electrically couple the third hardware interface to the first die.

公开(公告)号：US20230207471A1

公开(公告)日：2023-06-29

申请号：US17560609

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Omkar Karhade ,  Nitin Deshpande

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L23/5383 ,  H01L25/0655 ,  H01L23/481 ,  H01L24/08 ,  H01L25/50 ,  H01L24/80 ,  H01L2224/08235 ,  H01L2224/80815 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/16225

Abstract: Multi-die composite packages including directly bonded IC die and at least one electro-thermo-mechanical die (ETMD). An ETMD is distinguished from an active IC die as an ETMD is a passive die lacking any semiconductor devices, such as transistors. In exemplary embodiments, an ETMD includes a substrate, which may be a crystalline semiconductor material, for example, and one or more through substrate vias (TSVs) passing through a thickness of the substrate. The TSVs may enable a ETMD to electrically interconnect an (active) IC die of a composite package to another IC die of the package or to a package host.

公开(公告)号：US20230197637A1

公开(公告)日：2023-06-22

申请号：US17554471

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Mohammad Enamul Kabir ,  Nitin Deshpande ,  Omkar Karhade ,  Arnab Sarkar ,  Sairam Agraharam ,  Christopher Pelto ,  Gwang-Soo Kim ,  Ravindranath Mahajan

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L23/564 ,  H01L25/0655 ,  H01L21/447

Abstract: Stacked die assemblies having a moisture sealant layer according to embodiments are described herein. A microelectronic package structure having a first die with a second and an adjacent third die on the first die. Each of the second and third die comprise hybrid bonding interfaces with the first die. A first layer is on a region of the first die adjacent sidewalls of the second and the third dies, and adjacent an edge portion of the first die. The first layer comprises a diffusion barrier material A second layer is over the first layer, the second layer, wherein a top surface of the second layer is substantially coplanar with the top surfaces of the second and third dies. The first layer provides a hermetic moisture sealant layer for stacked die package structures.

公开(公告)号：US20230197546A1

公开(公告)日：2023-06-22

申请号：US17557925

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Omkar Karhade ,  Sairam Agraharam ,  Nitin Deshpande

IPC: H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L21/56

CPC classification number: H01L23/3114 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/16 ,  H01L25/0657 ,  H01L21/56 ,  H01L2224/32145 ,  H01L2225/06517

Abstract: Integrated circuit assemblies can be fabricated on a wafer scale, wherein a base template, having a plurality of openings, may cover a base substrate, such as a die wafer, wherein the base substrate has a plurality of first integrated circuit devices formed therein and wherein at least one second integrated circuit device is electrically attached to a corresponding first integrated circuit device through a respective opening in the base template. Thus, when the base substrate and base template are singulated into individual integrated circuit assemblies, the individual integrated circuit assemblies will each have a first integrated circuit that is edge aligned to a singulated portion of the base template. The singulated portion of the base template can provide an improved thermal path, mechanical strength, and/or electrical paths for the individual integrated circuit assemblies.

公开(公告)号：US20230194783A1

公开(公告)日：2023-06-22

申请号：US17557648

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Kaveh Hosseini ,  Omkar Karhade ,  Xiaoqian Li ,  Chia-Pin Chiu ,  Finian G. Rogers

IPC: G02B6/122 ,  G02B6/12

CPC classification number: G02B6/122 ,  G02B6/12004 ,  G02B2006/12102

Abstract: An electronic device may include a photonic integrated circuit (PIC) coupled with a substrate. The PIC may communicate a photonic signal with one or more optical fibers. The PIC may process the photonic signal into an electronic signal. The PIC may extend between a first end and a second end. An electronic integrated circuit (EIC) may be coupled with the substrate. The EIC may communicate with the PIC. The EIC may transmit the electronic signal to the PIC. The EIC may receive the electronic signal from the PIC. The electronic device may include a lens assembly. The lens assembly may be coupled with the first end of the PIC. In an example, optical interconnects of the PIC are aligned with the lens assembly such that the lens assembly is configured to transmit the photonic signal communicated between PIC and the optical fibers.