公开(公告)号：US20140284375A1

公开(公告)日：2014-09-25

申请号：US14165030

申请日：2014-01-27

Applicant: Micron Technology, Inc.

Inventor： Warren M. Farnworth ,  Rickie C. Lake ,  William M. Hiatt

IPC: B23K1/20

CPC classification number: B23K1/20 ,  B23K1/0016 ,  B23K35/22 ,  H01L29/40 ,  H01L2224/05001 ,  H01L2224/11 ,  Y10T428/12493 ,  Y10T428/12708 ,  Y10T428/12889 ,  Y10T428/12896 ,  Y10T428/12903

Abstract: Microfeature workpieces having alloyed conductive structures, and associated methods are disclosed. A method in accordance with one embodiment includes applying a volume of material to a bond pad of a microfeature workpiece, with the volume of material including a first metallic constituent and the bond pad including a second constituent. The method can further include elevating a temperature of the volume of material while the volume of material is applied to the bond pad to alloy the first metallic constituent and the second metallic constituent so that the first metallic constituent is alloyed generally throughout the volume of material. A thickness of the bond pad can be reduced from an initial thickness T1 to a reduced thickness T2.

Abstract translation: 公开了具有合金导电结构的微型工件和相关方法。 根据一个实施例的方法包括将一定体积的材料施加到微特征工件的接合焊盘，其中所述材料的体积包括第一金属成分，并且所述接合焊盘包括第二成分。 该方法还可以包括升高材料体积的温度，同时将材料的体积施加到接合垫以使第一金属构件和第二金属构件合金，使得第一金属构件通常在整个体积的材料中合金化。 接合焊盘的厚度可以从初始厚度T1减小到减小的厚度T2。

公开(公告)号：US20140206203A1

公开(公告)日：2014-07-24

申请号：US14222281

申请日：2014-03-21

Applicant: Micron Technology, Inc.

Inventor： Warren M. Farnworth ,  Tongbi Jiang

IPC: H01L21/02

CPC classification number: H01L21/02203 ,  H01L21/02126 ,  H01L21/02282 ,  H01L21/02345 ,  H01L21/02354 ,  H01L21/31695 ,  H01L21/7682 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/00

Abstract: Semiconductor devices with porous insulative materials are disclosed. The porous insulative materials may include a consolidated material with voids dispersed therethrough. The voids may be defined by shells of microcapsules. The voids impart the dielectric materials with reduced dielectric constants and, thus, increased electrical insulation properties.

Abstract translation: 公开了具有多孔绝缘材料的半导体器件。 多孔绝缘材料可以包括具有分散在其中的空隙的固结材料。 空隙可以由微胶囊的壳定义。 空隙赋予介电材料具有降低的介电常数，从而提高电绝缘性能。

公开(公告)号：US20140206145A1

公开(公告)日：2014-07-24

申请号：US14222467

申请日：2014-03-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Owen R. Fay ,  Warren M. Farnworth ,  David R. Hembree

IPC: H01L23/00

CPC classification number: H01L23/5384 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/03444 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05017 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05551 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05611 ,  H01L2224/114 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/1161 ,  H01L2224/1162 ,  H01L2224/1182 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/11826 ,  H01L2224/11831 ,  H01L2224/11903 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13075 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13562 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13687 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73257 ,  H01L2224/81139 ,  H01L2224/81191 ,  H01L2224/81205 ,  H01L2224/81345 ,  H01L2224/81365 ,  H01L2224/81815 ,  H01L2224/81898 ,  H01L2224/831 ,  H01L2224/83141 ,  H01L2224/83193 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system in accordance with a particular embodiment includes a first semiconductor substrate having a first substrate material, and a penetrating structure carried by the first semiconductor substrate. The system further includes a second semiconductor substrate having a second substrate material with a preformed recess. The penetrating structure of the first semiconductor substrate is received in the recess of the second semiconductor substrate and is mechanically engaged with the recess and secured to the second semiconductor substrate.

Abstract translation: 公开了用于堆叠管芯的互连结构，包括贯穿硅通孔的穿透结构以及相关的系统和方法。 根据特定实施例的系统包括具有第一衬底材料的第一半导体衬底和由第一半导体衬底承载的穿透结构。 该系统还包括第二半导体衬底，该第二半导体衬底具有带有预制凹槽的第二衬底材料。 第一半导体衬底的穿透结构被容纳在第二半导体衬底的凹部中，并且与凹部机械地接合并固定到第二半导体衬底。

公开(公告)号：US20140083270A1

公开(公告)日：2014-03-27

申请号：US14093682

申请日：2013-12-02

Applicant: Micron Technology, Inc.

Inventor： Warren M. Farnworth ,  Tom A. Muntifering ,  Paul J. Clawson

IPC: B28D5/00 ,  B23K26/40 ,  B23Q15/22 ,  B26F3/00

CPC classification number: H01L22/20 ,  B23K26/03 ,  B23K26/042 ,  B23K26/044 ,  B23K26/40 ,  B23K2101/40 ,  B23K2103/50 ,  B23K2103/56 ,  B23Q15/22 ,  B26F3/004 ,  B28D5/0064 ,  H01L21/78 ,  Y10T83/141 ,  Y10T83/178 ,  Y10T83/538

Abstract: Methods and systems for imaging and cutting semiconductor wafers and other microelectronic device substrates are disclosed herein. In one embodiment, a system for singulating microelectronic devices from a substrate includes an X-ray imaging system having an X-ray source spaced apart from an X-ray detector. The X-ray source can emit a beam of X-rays through the substrate and onto the X-ray detector, and X-ray detector can generate an X-ray image of at least a portion of the substrate. A method in accordance with another embodiment includes detecting spacing information for irregularly spaced dies of a semiconductor workpiece. The method can further include automatically controlling a process for singulating the dies of the semiconductor workpiece, based at least in part on the spacing information. For example, individual dies can be singulated from a workpiece via non-straight line cuts and/or multiple cutter passes.

Abstract translation: 本文公开了用于成像和切割半导体晶片和其它微电子器件基板的方法和系统。 在一个实施例中，用于从衬底分离微电子器件的系统包括具有与X射线检测器间隔开的X射线源的X射线成像系统。 X射线源可以通过衬底和X射线检测器发射X射线束，并且X射线检测器可以产生至少部分衬底的X射线图像。 根据另一实施例的方法包括检测半导体工件的不规则间隔的管芯的间隔信息​​。 该方法还可以包括至少部分地基于间隔信息来自动控制用于对半导体工件的管芯进行分割的工艺。 例如，可以通过非直线切割和/或多个切割器通过从工件分离各个模具。