公开(公告)号：US08067700B2

公开(公告)日：2011-11-29

申请号：US11927710

申请日：2007-10-30

申请人： Yu-Chang Pai ,  Shou-Kuo Hsu ,  Chien-Hung Liu

发明人： Yu-Chang Pai ,  Shou-Kuo Hsu ,  Chien-Hung Liu

IPC分类号： H05K1/11

CPC分类号： H05K1/0251 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/09718

摘要： A printed circuit board (200) includes at least one via (280) defined therein, the via has an upper cap (220) formed on a top surface of the PCB, and a lower cap (240) formed on a bottom surface of the PCB. A conductive hole (290) is defined in the PCB having a plated sidewall (230) plated on its inner surface, and a first clearance hole (271) is defined in a first inner layer (260) of the PCB around the sidewall. A first transmission line (210) defined on the top surface of the PCB is coupled to the upper cap, a first void (273) extending from a boundary of the first clearance hole being disposed along the layout direction of the first transmission line.

摘要翻译： 印刷电路板（200）包括限定在其中的至少一个通孔（280），所述通孔具有形成在所述PCB的顶表面上的上盖（220）和形成在所述PCB的底表面上的下盖（240） PCB。 导电孔（290）限定在印刷电路板中，电镀侧壁（230）镀在其内表面上，第一间隙孔限定在PCB的围绕侧壁的第一内层（260）中。 限定在PCB的顶表面上的第一传输线（210）联接到上盖，沿着第一传输线的布置方向布置的从第一间隙孔的边界延伸的第一空隙（273）。

公开(公告)号：US20090056983A1

公开(公告)日：2009-03-05

申请号：US11941979

申请日：2007-11-19

申请人： Chien-Hung Liu ,  Shou-Kuo Hsu ,  Yu-Chang Pai

发明人： Chien-Hung Liu ,  Shou-Kuo Hsu ,  Yu-Chang Pai

IPC分类号： H05K1/02

CPC分类号： H05K1/0245 ,  H05K1/0298 ,  H05K2201/09236 ,  H05K2201/09336 ,  H05K2201/09672 ,  Y10S439/941

摘要： A printed circuit board (PCB) includes first and second signal layers sandwiching a dielectric layer therebetween and a first differential pair and a second differential pair each having a positive differential trace and a negative differential trace. The positive differential traces of the two differential pairs are disposed within the first signal layer. The negative differential traces of the two differential pairs are disposed within the second signal layer. The positive differential trace of the first differential pair is defined at the left side of the positive differential trace of the second differential pair. The negative differential trace of the first differential pair is defined at the right side of the negative differential trace of the second differential pair.

摘要翻译： 印刷电路板（PCB）包括夹在其间的电介质层的第一和第二信号层，以及分别具有正差分迹线和负差分迹线的第一差分对和第二差分对。 两个差分对的正差分迹线设置在第一信号层内。 两个差分对的负差分迹线设置在第二信号层内。 第一差分对的正差分迹线被定义在第二差分对的正差分迹线的左侧。 第一差分对的负差分迹线被限定在第二差分对的负差分迹线的右侧。

公开(公告)号：US07635814B2

公开(公告)日：2009-12-22

申请号：US11941979

申请日：2007-11-19

申请人： Chien-Hung Liu ,  Shou-Kuo Hsu ,  Yu-Chang Pai

发明人： Chien-Hung Liu ,  Shou-Kuo Hsu ,  Yu-Chang Pai

IPC分类号： H05K1/00

CPC分类号： H05K1/0245 ,  H05K1/0298 ,  H05K2201/09236 ,  H05K2201/09336 ,  H05K2201/09672 ,  Y10S439/941

摘要： A printed circuit board (PCB) includes first and second signal layers sandwiching a dielectric layer therebetween and a first differential pair and a second differential pair each having a positive differential trace and a negative differential trace. The positive differential traces of the two differential pairs are disposed within the first signal layer. The negative differential traces of the two differential pairs are disposed within the second signal layer. The positive differential trace of the first differential pair is defined at the left side of the positive differential trace of the second differential pair. The negative differential trace of the first differential pair is defined at the right side of the negative differential trace of the second differential pair.

摘要翻译： 印刷电路板（PCB）包括夹在其间的电介质层的第一和第二信号层，以及分别具有正差分迹线和负差分迹线的第一差分对和第二差分对。 两个差分对的正差分迹线设置在第一信号层内。 两个差分对的负差分迹线设置在第二信号层内。 第一差分对的正差分迹线被定义在第二差分对的正差分迹线的左侧。 第一差分对的负差分迹线被限定在第二差分对的负差分迹线的右侧。

公开(公告)号：US09181084B2

公开(公告)日：2015-11-10

申请号：US12652715

申请日：2010-01-05

申请人： Chien-Hung Liu

发明人： Chien-Hung Liu

IPC分类号： H01L23/02 ,  B81C1/00 ,  H01L21/683 ,  H01L23/00

CPC分类号： B81C1/00325 ,  B81B2207/092 ,  B81B2207/097 ,  B81C1/00301 ,  B81C2201/0115 ,  B81C2203/0118 ,  H01L21/6835 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/93 ,  H01L2221/68304 ,  H01L2221/68331 ,  H01L2221/6834 ,  H01L2221/68372 ,  H01L2221/68377 ,  H01L2221/68386 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/11009 ,  H01L2224/11019 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/29007 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/93 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/10156 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15788 ,  H01L2224/0231 ,  H01L2224/11 ,  H01L2224/13099 ,  H01L2924/00

摘要： The invention provides an electronic device package and fabrication method thereof. The electronic device package includes a sensor chip. An upper surface of the sensor chip comprises a sensing film. A covering plate having an opening structure covers the upper surface of the sensor chip. A cavity is between the covering plate and the sensor chip, corresponding to a position of the sensing film, where the cavity communicates with the opening structure. A spacer is between the covering plate and the sensor chip, surrounding the cavity. A pressure releasing region is between the spacer and the sensing film.

摘要翻译： 本发明提供一种电子器件封装及其制造方法。 电子装置封装包括传感器芯片。 传感器芯片的上表面包括感测膜。 具有开口结构的覆盖板覆盖传感器芯片的上表面。 覆盖板和传感器芯片之间的腔体对应于感测膜的位置，其中空腔与开口结构连通。 间隔件位于覆盖板和传感器芯片之间，围绕腔体。 压力释放区域位于间隔件和感测膜之间。

公开(公告)号：US08748949B2

公开(公告)日：2014-06-10

申请号：US12940607

申请日：2010-11-05

申请人： Chien-Hung Liu ,  Cheng-Te Chou

发明人： Chien-Hung Liu ,  Cheng-Te Chou

IPC分类号： H01L23/48 ,  H01L21/70 ,  H01L29/40

CPC分类号： H01L27/14618 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/93 ,  H01L24/94 ,  H01L25/0657 ,  H01L27/14683 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/051 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/05638 ,  H01L2224/05688 ,  H01L2224/13022 ,  H01L2224/29007 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32052 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/01014 ,  H01L2924/053 ,  H01L2924/01 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

摘要： The invention provides a chip package and fabrication method thereof. In one embodiment, the chip package includes: a semiconductor substrate having opposite first and second surfaces, at least one bond pad region and at least one device region; a plurality of conductive pad structures disposed on the bond pad region at the first surface of the semiconductor substrate; a plurality of heavily doped regions isolated from one another, underlying and electrically connected to the conductive pad structures; and a plurality of conductive bumps underlying the heavily doped regions and electrically connected to the conductive pad structures through the heavily-doped regions.

摘要翻译： 本发明提供一种芯片封装及其制造方法。 在一个实施例中，芯片封装包括：具有相对的第一和第二表面，至少一个焊盘区域和至少一个器件区域的半导体衬底; 多个导电焊盘结构，设置在半导体衬底的第一表面处的焊盘区域上; 多个彼此隔离的重掺杂区域，其下面并电连接到导电焊盘结构; 以及在重掺杂区域下面的多个导电凸块，并通过重掺杂区域电连接到导电焊盘结构。

公开(公告)号：US08614488B2

公开(公告)日：2013-12-24

申请号：US13314114

申请日：2011-12-07

申请人： Ying-Nan Wen ,  Ho-Yin Yiu ,  Yen-Shih Ho ,  Shu-Ming Chang ,  Chien-Hung Liu ,  Shih-Yi Lee ,  Wei-Chung Yang

发明人： Ying-Nan Wen ,  Ho-Yin Yiu ,  Yen-Shih Ho ,  Shu-Ming Chang ,  Chien-Hung Liu ,  Shih-Yi Lee ,  Wei-Chung Yang

IPC分类号： H01L21/70

CPC分类号： H01L21/76898 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3185 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2221/68363 ,  H01L2224/02372 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05672 ,  H01L2224/11002 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/96 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/05552

摘要： A chip package includes: a substrate; a drain and a source regions located in the substrate; a gate located on or buried in the substrate; a drain conducting structure, a source conducting structure, and a gate conducting structure, disposed on the substrate and electrically connected to the drain region, the source region, and the gate, respectively; a second substrate disposed beside the substrate; a second drain and a second source region located in the second substrate, wherein the second drain region is electrically connected to the source region; a second gate located on or buried in the second substrate; and a second source and a second gate conducting structure disposed on the second substrate and electrically connected to the second source region and the second gate, respectively, wherein terminal points of the drain, the source, the gate, the second source, and the second gate conducting structures are substantially coplanar.

摘要翻译： 芯片封装包括：基板; 位于衬底中的漏极和源极区域; 位于衬底上或埋在衬底中的门; 漏极导电结构，源极导电结构和栅极导电结构，分别设置在所述衬底上并电连接到所述漏极区域，所述源极区域和所述栅极; 设置在所述基板旁边的第二基板; 位于所述第二基板中的第二漏极和第二源极区域，其中所述第二漏极区域电连接到所述源极区域; 位于第二基板上或埋在第二基板中的第二栅极; 以及第二源极和第二栅极导电结构，其设置在所述第二基板上并分别电连接到所述第二源极区域和所述第二栅极，其中所述漏极，所述源极，所述栅极，所述第二源极和所述第二栅极的端点 栅极导电结构基本上共面。

公开(公告)号：US08362515B2

公开(公告)日：2013-01-29

申请号：US13081346

申请日：2011-04-06

申请人： Chia-Ming Cheng ,  Chien-Hung Liu

发明人： Chia-Ming Cheng ,  Chien-Hung Liu

IPC分类号： H01L33/00

CPC分类号： H01L23/49805 ,  H01L21/76898 ,  H01L23/13 ,  H01L23/481 ,  H01L23/50 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2924/0002 ,  H01L2924/01021 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05552

摘要： An embodiment of the invention provides a chip package which includes a substrate having an upper surface and a lower surface and having at least a side surface, and at least a trench extending from the upper surface towards the lower surface and extending from the side surface towards an inner portion of the substrate, wherein a width of the trench near the upper surface is not equal to a width of the trench near the lower surface, and at least an insulating layer located on a sidewall of the trench, and at least a conducting pattern located on the insulating layer, wherein the side surface is separated from the conducting pattern in the trench by a predetermined distance such that a portion of the insulating layer is exposed, and at least a conducting region electrically connected to the conducting pattern.

摘要翻译： 本发明的一个实施例提供了一种芯片封装，其包括具有上表面和下表面的基板，并且至少具有一个侧表面，以及至少一个从上表面向下表面延伸并且从侧表面向着 衬底的内部部分，其中靠近上表面的沟槽的宽度不等于下表面附近的沟槽的宽度，以及至少位于沟槽的侧壁上的绝缘层，并且至少导电 位于所述绝缘层上，其中所述侧表面与所述沟槽中的导电图案分离预定距离，使得所述绝缘层的一部分露出，以及至少导电区域电连接到所述导电图案。

公开(公告)号：US20120274870A1

公开(公告)日：2012-11-01

申请号：US13549798

申请日：2012-07-16

申请人： Chien-Hung Liu

发明人： Chien-Hung Liu

IPC分类号： G02F1/1343

CPC分类号： G02F1/136259 ,  G02F2001/136263

摘要： One aspect of the present disclosure relates to a common repair structure for repairing scanning and/or data line defects in a liquid crystal display panel. In one embodiment, the common repair structure includes a plurality of “H” shaped structures, where each “H” shaped structure is placed over a corresponding segment of two neighboring scanning lines located between and associated with two neighboring pixels along the second direction or a corresponding segment of two neighboring data lines located between and associated with two neighboring pixels along the first direction.

摘要翻译： 本公开的一个方面涉及用于修复液晶显示面板中的扫描和/或数据线缺陷的常见修复结构。 在一个实施例中，公共修复结构包括多个H形结构，其中每个H形结构放置在沿着第二方向位于两个相邻像素之间并且与两个相邻像素相关联的两个相邻扫描线的对应段上，或者相应的二段 位于沿与第一方向相邻的两个相邻像素之间并与之相关联的相邻数据线。

公开(公告)号：US08264631B2

公开(公告)日：2012-09-11

申请号：US12616420

申请日：2009-11-11

申请人： Chien-Hung Liu

发明人： Chien-Hung Liu

IPC分类号： G02F1/1333

CPC分类号： G02F1/136259 ,  G02F2001/136263

摘要： One aspect of the present disclosure relates to a common repair structure for repairing scanning and/or data line defects in a liquid crystal display panel. In one embodiment, the common repair structure includes a plurality of “H” shaped structures, where each “H” shaped structure is placed over a corresponding segment of two neighboring scanning lines located between and associated with two neighboring pixels along the second direction or a corresponding segment of two neighboring data lines located between and associated with two neighboring pixels along the first direction.

摘要翻译： 本公开的一个方面涉及用于修复液晶显示面板中的扫描和/或数据线缺陷的常见修复结构。 在一个实施例中，公共修复结构包括多个“H”形结构，其中每个“H”形结构被放置在沿着第二方向位于两个相邻像素之间并与之相关联的两个相邻扫描线的对应段上，或者 两个相邻数据线的对应段位于沿着第一方向的两个相邻像素之间并与之相关联。

公开(公告)号：US20120156320A1

公开(公告)日：2012-06-21

申请号：US12971466

申请日：2010-12-17

申请人： Wen-Yuh Jywe ,  Jing-Chung Shen ,  Chin-Tien Yang ,  Chien-Hung Liu ,  Jau-Jiu Ju ,  Chia-Hung Wu ,  Chun-Chieh Huang ,  Lili Duan ,  Yuan-Chin Lee

发明人： Wen-Yuh Jywe ,  Jing-Chung Shen ,  Chin-Tien Yang ,  Chien-Hung Liu ,  Jau-Jiu Ju ,  Chia-Hung Wu ,  Chun-Chieh Huang ,  Lili Duan ,  Yuan-Chin Lee

IPC分类号： B29C59/16 ,  B29C37/00

CPC分类号： B23K26/0853

摘要： A manufacturing-process equipment has a platform assembly, a measurement feedback assembly and a laser-working assembly. The platform assembly has a base and a hybrid-moving platform. The base has a mounting frame. The hybrid-moving platform is mounted on the base and has a long-stroke moving stage and a piezo-driven micro-stage. The long-stroke moving stage has a benchmark set and a driving device. The piezo-driven micro-stage is connected to the long-stroke moving stage and has a working platform. The measurement feedback assembly is securely mounted on the platform assembly and has a laser interferometer, a reflecting device and a signal-receiving device. The laser-working assembly is mounted on the platform assembly, is electrically connected to the measurement feedback assembly and has a laser direct-writing head, a controlling interface device and a positioning interface device.

摘要翻译： 制造过程设备具有平台组件，测量反馈组件和激光加工组件。 平台组件具有基座和混合动力平台。 底座有一个安装架。 混合动力平台安装在基座上，具有长行程移动台和压电驱动微型平台。 长冲程移动台具有基准组和驱动装置。 压电驱动微型平台连接到长行程移动台，并具有工作平台。 测量反馈组件牢固地安装在平台组件上，并具有激光干涉仪，反射装置和信号接收装置。 激光加工组件安装在平台组件上，电连接到测量反馈组件，并具有激光直写头，控制接口装置和定位接口装置。