公开(公告)号：US09991388B2

公开(公告)日：2018-06-05

申请号：US15450305

申请日：2017-03-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Ching-Wei Tsai ,  Chi-Wen Liu ,  Chih-Hao Wang ,  Ying-Keung Leung

IPC分类号： H01L21/02 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8234

CPC分类号： H01L29/78618 ,  B82Y10/00 ,  H01L21/283 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/41708 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78651 ,  H01L29/78696 ,  H01L2029/7858

摘要： A device includes isolation regions extending into a semiconductor substrate, with a substrate strip between opposite portions of the isolation regions having a first width. A source/drain region has a portion overlapping the substrate strip, wherein an upper portion of the source/drain region has a second width greater than the first width. The upper portion of the source/drain region has substantially vertical sidewalls. A source/drain silicide region has inner sidewalls contacting the vertical sidewalls of the source/drain region.

公开(公告)号：US09978870B2

公开(公告)日：2018-05-22

申请号：US14949664

申请日：2015-11-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Chao-Hsiung Wang ,  Chi-Wen Liu ,  Guan-Lin Chen

IPC分类号： H01L21/70 ,  H01L29/772 ,  H01L21/336 ,  H01L21/335 ,  H01L29/78 ,  H01L29/66 ,  H01L29/161 ,  H01L29/165 ,  H01L21/762 ,  H01L29/10 ,  H01L29/06 ,  H01L29/16

CPC分类号： H01L29/7849 ,  H01L21/76205 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/785

摘要： A fin structure suitable for a FinFET and having a buried insulator layer is disclosed. In an exemplary embodiment, a semiconductor device comprises a substrate with a first semiconductor material and having a fin structure formed thereupon. The fin structure includes a lower region proximate to the substrate, a second semiconductor material disposed on the lower region, a third semiconductor material disposed on the second semiconductor material, and an insulating material selectively disposed on the second semiconductor material such that the insulating material electrically isolates a channel region of the fin structure and further such that the insulating material exerts a strain on the channel region. The semiconductor device further comprises an isolation feature disposed adjacent to the fin structure.

公开(公告)号：US20180097114A1

公开(公告)日：2018-04-05

申请号：US15819952

申请日：2017-11-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Shi Ning Ju ,  Ching-Wei Tsai ,  Chih-Hao Wang ,  Ying-Keung Leung ,  Carlos H. Diaz

IPC分类号： H01L29/78 ,  H01L29/24 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66

CPC分类号： H01L29/66545 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： A method includes forming a first hard mask over a semiconductor substrate, etching the semiconductor substrate to form recesses, with a semiconductor strip located between two neighboring ones of the recesses, forming a second hard mask on sidewalls of the semiconductor strip, performing a first anisotropic etch on the second hard mask to remove horizontal portions of the second hard mask, and performing a second anisotropic etch on the semiconductor substrate using the first hard mask and vertical portions of the second hard mask as an etching mask to extend the recesses down. The method further includes removing the vertical portions of the second hard mask, and forming isolation regions in the recesses. The isolation regions are recessed, and a portion of the semiconductor strip between the isolation regions protrudes higher than the isolation regions to form a semiconductor fin.

公开(公告)号：US09935011B2

公开(公告)日：2018-04-03

申请号：US14851535

申请日：2015-09-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Ting-Hung Hsu ,  Chao-Hsiung Wang ,  Chi-Wen Liu

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/165 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L27/12 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L21/762

CPC分类号： H01L21/0217 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： A method includes forming Shallow Trench Isolation (STI) regions in a semiconductor substrate and a semiconductor strip between the STI regions. The method also include replacing a top portion of the semiconductor strip with a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer has a first germanium percentage higher than a second germanium percentage of the second semiconductor layer. The method also includes recessing the STI regions to form semiconductor fins, forming a gate stack over a middle portion of the semiconductor fin, and forming gate spacers on sidewalls of the gate stack. The method further includes forming fin spacers on sidewalls of an end portion of the semiconductor fin, recessing the end portion of the semiconductor fin, and growing an epitaxial region over the end portion of the semiconductor fin.

公开(公告)号：US09882032B2

公开(公告)日：2018-01-30

申请号：US15401867

申请日：2017-01-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Zhiqiang Wu ,  Carlos H Diaz

IPC分类号： H01L29/66 ,  H01L29/51 ,  H01L29/423 ,  H01L29/78 ,  H01L29/10 ,  H01L21/02 ,  H01L21/225 ,  H01L21/28

CPC分类号： H01L29/66818 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/2255 ,  H01L21/28167 ,  H01L29/1054 ,  H01L29/42364 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7849 ,  H01L29/785

摘要： A method includes forming isolation features on a substrate, thereby defining an active region on the semiconductor substrate; recessing the active region to form a fin trench; forming a fin feature on the fin trench by growing a first semiconductor layer on the substrate and a second semiconductor layer on the first semiconductor layer; performing a first recessing process; forming a dummy gate stack over the fin feature and the isolation feature; performing a thermal oxidation process to selectively oxidize the first semiconductor layer to form a semiconductor oxide feature on sidewalls of the first semiconductor layer; performing a second recessing process such that a portion of the isolation feature is recessed to below the second semiconductor layer, resulting in a dented void overlying the semiconductor oxide feature and underlying the second semiconductor layer; and forming a gate stack including a gate dielectric layer extending to the dented void.

公开(公告)号：US09871141B2

公开(公告)日：2018-01-16

申请号：US15090099

申请日：2016-04-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Carlos H. Diaz ,  Chih-Hao Wang ,  Gwan Sin Chang ,  Jean-Pierre Colinge ,  Kuo-Cheng Ching ,  Zhiqiang Wu

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66

CPC分类号： H01L29/7849 ,  H01L21/02104 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

摘要： A method includes performing a first epitaxy to grow a silicon germanium layer over a semiconductor substrate, performing a second epitaxy to grow a silicon layer over the silicon germanium layer, and performing a first oxidation to oxidize the silicon germanium layer, wherein first silicon germanium oxide regions are generated. A strain releasing operation is performed to release a strain caused by the first silicon germanium oxide regions. A gate dielectric is formed on a top surface and a sidewall of the silicon layer. A gate electrode is formed over the gate dielectric.

公开(公告)号：US09847332B2

公开(公告)日：2017-12-19

申请号：US15263593

申请日：2016-09-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Ting-Hung Hsu

IPC分类号： H01L29/78 ,  H01L29/775 ,  H01L29/06 ,  H01L21/28 ,  H01L21/336 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/786 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161

CPC分类号： H01L27/0921 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823892 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696

摘要： The present disclosure provides a method for fabricating an integrated circuit device. The method includes providing a precursor including a substrate having first and second metal-oxide-semiconductor (MOS) regions. The first and second MOS regions include first and second gate regions, semiconductor layer stacks, and source/drain regions respectively. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the first gate region to form first outer oxide layer and inner nanowire set, and exposing the first inner nanowire set. A first high-k/metal gate (HK/MG) stack wraps around the first inner nanowire set. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the second gate region to form second outer oxide layer and inner nanowire set, and exposing the second inner nanowire set. A second HK/MG stack wraps around the second inner nanowire set.

公开(公告)号：US09806178B2

公开(公告)日：2017-10-31

申请号：US15374963

申请日：2016-12-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Guan-Lin Chen ,  Chao-Hsiung Wang ,  Chi-Wen Liu

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306

CPC分类号： H01L29/66795 ,  H01L21/02236 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/30625 ,  H01L29/785

摘要： A method comprises recessing a substrate to form a fin enclosed by an isolation region, wherein the substrate is formed of a first semiconductor material, recessing the fin to form a trench over a lower portion of the fin, growing a second semiconductor material in the trench to form a middle portion of the fin through a first epitaxial process, forming a first carbon doped layer over the lower portion through a second epitaxial process, growing the first semiconductor material over the first carbon doped layer to form an upper portion of the fin through a third epitaxial process, forming a first source/drain region through a fourth epitaxial process, wherein a second carbon doped layer is formed underlying the first source/drain region and applying a thermal oxidation process to the middle portion of the fin to form an oxide outer layer.

公开(公告)号：US09721955B2

公开(公告)日：2017-08-01

申请号：US14262378

申请日：2014-04-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Ka-Hing Fung ,  Chih-Sheng Chang ,  Zhiqiang Wu

IPC分类号： H01L27/092 ,  H01L27/11 ,  H01L29/161 ,  H01L29/78 ,  H01L21/02 ,  H01L21/033 ,  H01L21/324 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51

CPC分类号： H01L27/1104 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/0332 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0924 ,  H01L29/161 ,  H01L29/165 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

摘要： The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a substrate having an n-type FinFET (NFET) region and a p-type FinFET (PFET) region. The device also includes a first and a second fin structures over the substrate in the NFET region and a third fin structure over the substrate in the PFET region. The device also includes a first high-k (HK)/metal gate (MG) stack in the NFET region, including wrapping over a portion of the first fin structure, a first subset of the first source/drain (S/D) features, adjacent to the first HK/MG stack, over the recessed first fin structure and a second subset of the first S/D features partially over the recessed second fin structure and partially over the recessed first fin structure.

公开(公告)号：US09711533B2

公开(公告)日：2017-07-18

申请号：US14885115

申请日：2015-10-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Kuo-Cheng Ching ,  Ching-Wei Tsai ,  Chih-Hao Wang ,  Ying-Keung Leung

IPC分类号： H01L27/118 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

CPC分类号： H01L27/11807 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/32135 ,  H01L21/32155 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66803 ,  H01L29/7851 ,  H01L2027/11853 ,  H01L2027/11864

摘要： A semiconductor device includes a first FinFET device and a second FinFET device. The first FinFET device includes a first gate, a first source, and a first drain. The first FinFET device has a first source/drain proximity. The second FinFET device includes a second gate, a second source, and a second drain. The second FinFET device has a second source/drain proximity that is smaller than the first source/drain proximity. In some embodiments, \the first FinFET device is an Input/Output (I/O) device, and the second FinFET device is a non-I/O device such as a core device. In some embodiments, the greater source/drain proximity of the first FinFET device is due to an extra spacer of the first FinFET device that does not exist for the second FinFET device.