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    Non-volatile semiconductor memory device with power-saving feature
    22.
    发明授权
    Non-volatile semiconductor memory device with power-saving feature 有权
    具有省电功能的非易失性半导体存储器件

    公开(公告)号：US09213389B2

    公开(公告)日：2015-12-15

    申请号：US13617908

    申请日：2012-09-14

    Applicant: HakJune Oh

    Inventor： HakJune Oh

    IPC: G06F1/26 ,  G06F1/32 ,  G06F1/12 ,  G11C16/16 ,  G11C16/32

    CPC classification number: G06F1/3203 ,  G06F1/12 ,  G06F1/3275 ,  G11C16/16 ,  G11C16/32 ,  Y02D10/14

    Abstract: A non-volatile semiconductor memory device, comprising: an interface for receiving commands issued by a controller, the commands including an erase command; a functional entity with circuit components and having a terminal; a node; switchable circuitry capable of controllably switching between a first operational state in which the terminal is electrically connected to the node and a second operational state in which the terminal is electrically decoupled from the node, the node being configured to have a signal for the functional entity communicated through it when the switchable circuitry is in the first operational state; and a command processing unit configured to recognize the commands issued by the controller and, in response to recognizing the erase command, to cause the switchable circuitry to switch from the first operational state to the second operational state.

    Abstract translation: 一种非易失性半导体存储器件，包括：用于接收由控制器发出的命令的接口，所述命令包括擦除命令; 具有电路组件并具有终端的功能实体; 一个节点 能够在端子与节点电连接的第一操作状态和端子与节点电分离的第二操作状态之间可控地切换的可切换电路，该节点被配置为具有用于功能实体通信的信号 当可切换电路处于第一操作状态时; 以及命令处理单元，其被配置为识别由所述控制器发出的命令，并且响应于识别所述擦除命令，使所述可切换电路从所述第一操作状态切换到所述第二操作状态。

    Composite semiconductor memory device with error correction
    24.
    发明授权
    Composite semiconductor memory device with error correction 有权
    具有误差校正的复合半导体存储器件

    公开(公告)号：US09098430B2

    公开(公告)日：2015-08-04

    申请号：US13038461

    申请日：2011-03-02

    Applicant: Jin-Ki Kim

    Inventor： Jin-Ki Kim

    IPC: G11C29/00 ,  G06F11/10 ,  G11C29/04

    CPC classification number: G06F11/1044 ,  G06F11/1048 ,  G11C2029/0411 ,  H03M13/05 ,  H03M13/611

    Abstract: A composite semiconductor memory device, comprising: a plurality of nonvolatile memory devices; and an interface device connected to the plurality of nonvolatile memory devices and for connection to a memory controller, the interface device comprising an error correction coding (ECC) engine. Also, a memory system, comprising: a memory controller; and at least one composite semiconductor memory device configured for being written to and read from by the memory controller and comprising a built-in error correction coding (ECC) engine. Also, a memory system, comprising: a composite semiconductor memory device comprising a plurality of nonvolatile memory devices; and a memory controller connected to the at least one composite semiconductor memory device, for issuing read and write commands to the composite semiconductor memory device to cause data to be written to or read from individual ones of the nonvolatile memory devices; the composite semiconductor memory device providing error-free writing and reading of the data.

    Abstract translation: 一种复合半导体存储器件，包括：多个非易失性存储器件; 以及连接到所述多个非易失性存储器件并且用于连接到存储器控制器的接口设备，所述接口设备包括纠错编码（ECC）引擎。 另外，一种存储器系统，包括：存储器控制器; 以及至少一个复合半导体存储器件，被配置为被存储器控制器写入和读出，并且包括内置纠错编码（ECC）引擎。 另外，一种存储系统，包括：复合半导体存储器件，其包括多个非易失性存储器件; 以及存储器控制器，连接到所述至少一个复合半导体存储器件，用于向所述复合半导体存储器件发出读取和写入命令，以使数据被写入或从所述非易失性存储器件中的各个写入; 所述复合半导体存储器件提供无错误的写入和读取数据。

    Nonvolatile memory with split substrate select gates and hierarchical bitline configuration
    26.
    发明授权
    Nonvolatile memory with split substrate select gates and hierarchical bitline configuration 有权
    具有分离衬底选择门和分级位线配置的非易失性存储器

    公开(公告)号：US09007834B2

    公开(公告)日：2015-04-14

    申请号：US13830054

    申请日：2013-03-14

    Applicant: Mosaid Technologies Incorporated

    Inventor： Hyoung Seub Rhie

    IPC: G11C16/04 ,  G11C11/56 ,  G11C16/14

    CPC classification number: G11C11/5635 ,  G11C16/0483 ,  G11C16/14

    Abstract: Generally, the present disclosure provides a non-volatile memory device having a hierarchical bitline structure for preventing erase voltages applied to one group of memory cells of the memory array from leaking to other groups in which erasure is not required. Local bitlines are coupled to the memory cells of each group of memory cells. Each local bitline can be selectively connected to a global bitline during read operations for the selected group, and all the local bitlines can be disconnected from the global bitline during an erase operation when a specific group is selected for erasure. Select devices for electrically connecting each bitline of a specific group of memory cells to the global bitline have device bodies that are electrically isolated from the bodies of those memory cells.

    Abstract translation: 通常，本公开提供了一种具有分级位线结构的非易失性存储器件，用于防止施加到存储器阵列的一组存储器单元的擦除电压泄漏到不需要擦除的其他组。 本地位线耦合到每组存储器单元的存储单元。 每个本地位线可以在所选择的组的读取操作期间选择性地连接到全局位线，并且当选择特定组以进行擦除时，在擦除操作期间，可以将全局位线与全局位线断开。 选择用于将特定组存储器单元的每个位线电连接到全局位线的器件具有与这些存储器单元的主体电隔离的器件体。

    Through Semiconductor via Structure with Reduced Stress Proximity Effect
    29.
    发明申请
    Through Semiconductor via Structure with Reduced Stress Proximity Effect 审中-公开
    通过半导体通过结构减少应力接近效应

    公开(公告)号：US20150021773A1

    公开(公告)日：2015-01-22

    申请号：US14312052

    申请日：2014-06-23

    Applicant: Conversant Intellectual Property Management Inc.

    Inventor： Soogeun Lee

    IPC: H01L23/48 ,  H01L21/768

    CPC classification number: H01L23/481 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated circuit device and associated fabrication process are disclosed for forming a through semiconductor via (TSV) conductor structure in a semiconductor substrate with active circuitry formed on a first substrate surface where the TSV conductor structure includes multiple small diameter conductive vias extending through the first substrate surface and into the semiconductor substrate by a predetermined depth and a large diameter conductive via formed to extend from the multiple small diameter conductive vias and through a second substrate surface opposite to the first substrate surface.

    Abstract translation: 公开了一种用于在半导体衬底中形成贯穿半导体通孔（TSV）导体结构的集成电路器件和相关的制造工艺，其中有源电路形成在第一衬底表面上，其中TSV导体结构包括延伸穿过第一衬底的多个小直径导电通孔 表面并通过形成为从多个小直径导电通孔延伸并通过与第一衬底表面相对的第二衬底表面的预定深度和大直径导电通孔进入半导体衬底。

    Data processing with time-based memory access
    30.
    发明授权
    Data processing with time-based memory access 有权
    数据处理与基于时间的内存访问

    公开(公告)号：US08914612B2

    公开(公告)日：2014-12-16

    申请号：US11978529

    申请日：2007-10-29

    Applicant: Nagi N. Mekhiel

    Inventor： Nagi N. Mekhiel

    IPC: G06F13/00 ,  G06F12/06

    CPC classification number: G06F12/06 ,  G06F2212/1016

    Abstract: Memory access in data processing is provided using a time-based technique in which memory locations are mapped to respectively corresponding periods of time during which they are made available for access.

    Abstract translation: 使用基于时间的技术来提供数据处理中的存储器访问，其中存储器位置被映射到分别对应的可用于访问的时间段。

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