公开(公告)号：US09240466B2

公开(公告)日：2016-01-19

申请号：US14451174

申请日：2014-08-04

Applicant: STMicroelectronics SA ,  STMicroelectronics, Inc.

Inventor： Pierre Morin ,  Denis Rideau ,  Olivier Nier

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/02 ,  H01L21/324 ,  H01L21/762 ,  H01L29/78 ,  H01L27/12

CPC classification number: H01L29/66772 ,  H01L21/0217 ,  H01L21/324 ,  H01L21/76283 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/785

Abstract: The disclosure concerns a method of stressing a semiconductor layer comprising: forming, over a silicon on insulator structure having a semiconductor layer in contact with an insulating layer, one or more stressor blocks aligned with first regions of said semiconductor layer in which transistor channels are to be formed, wherein said stressor blocks are stressed such that they locally stress said semiconductor layer; and deforming second regions of said insulating layer adjacent to said first regions by temporally decreasing, by annealing, the viscosity of said insulator layer.

Abstract translation: 本公开涉及一种对半导体层施加应力的方法，包括：在绝缘体上的结构上形成绝缘体结构，该绝缘体上硅结构具有与绝缘层相接触的半导体层，一个或多个与晶体管沟道所在半导体层的第一区对准的应力块 形成，其中所述应力块被应力，使得它们局部应力所述半导体层; 以及通过退火所述绝缘体层的粘度暂时减小所述绝缘层的与所述第一区域相邻的第二区域。

公开(公告)号：US09231642B2

公开(公告)日：2016-01-05

申请号：US14191037

申请日：2014-02-26

Applicant: STMicroelectronics SA

Inventor： Baudouin Martineau ,  Olivier Richard ,  Frederic Gianesello

IPC: H04B1/44 ,  H04B1/40 ,  H01P5/12 ,  H01P5/16 ,  H01Q3/40 ,  H01Q25/00 ,  H03F3/24 ,  H03F3/60 ,  H03F3/68 ,  H03F3/189 ,  H03F3/20

CPC classification number: H01P5/12 ,  H01P5/16 ,  H01Q3/40 ,  H01Q25/00 ,  H03F3/189 ,  H03F3/19 ,  H03F3/20 ,  H03F3/211 ,  H03F3/24 ,  H03F3/602 ,  H03F3/68 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2203/21106 ,  H04B1/40

Abstract: A multichannel splitter formed from 1 to 2 splitters. An input terminal of a first 1 to 2 splitter defines an input of the multichannel splitter. The 1 to 2 splitters are electrically series-connected. First respective outputs of the 1 to 2 splitters define output terminals of the multichannel splitter.

Abstract translation: 一个由1到2个分路器组成的多通道分路器。 第一个1到2个分配器的输入端定义了多通道分离器的输入。 1至2个分离器电气串联连接。 1到2个分路器的第一个相应的输出定义了多通道分路器的输出端子。

公开(公告)号：US09224708B2

公开(公告)日：2015-12-29

申请号：US14339630

申请日：2014-07-24

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA

Inventor： Jean-Philippe Colonna ,  Perceval Coudrain

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L21/306 ,  H01L21/48 ,  H01L23/31 ,  H01L21/683

CPC classification number: H01L24/19 ,  H01L21/30604 ,  H01L21/4853 ,  H01L21/6836 ,  H01L21/7685 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/20 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/13009 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13084 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13181 ,  H01L2224/13186 ,  H01L2224/1356 ,  H01L2224/13565 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13681 ,  H01L2224/13686 ,  H01L2224/14181 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The invention relates to a method for producing an interconnection pad on a conducting element comprising an upper face and a side wall; the method being executed from a substrate at least the upper face of which is insulating; the conducting element going through at least an insulating portion of the substrate, the method being characterized in that it comprises the sequence of the following steps: a step of embossing the conducting element, a step of forming, above the upper insulating face of the substrate, a stack of layers comprising at least one electrically conducting layer and one electrically resistive layer, a step of partially removing the electrically resistive layer, a step of electrolytic growth on the portion of the electrically conducting layer so as to form at least one interconnection pad on said conducting element.

Abstract translation: 本发明涉及一种用于在导电元件上制造互连焊盘的方法，包括上表面和侧壁; 所述方法从至少其上表面绝缘的衬底执行; 所述导电元件至少穿过所述基板的绝缘部分，所述方法的特征在于，其包括以下步骤的顺序：对所述导电元件进行压花的步骤，在所述基板的上绝缘面上方形成步骤 ，包括至少一个导电层和一个电阻层的层叠层，部分去除所述电阻层的步骤，在所述导电层的所述部分上的电解生长步骤，以便形成至少一个互连衬垫 在所述导电元件上。

公开(公告)号：US20150279883A1

公开(公告)日：2015-10-01

申请号：US14660847

申请日：2015-03-17

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Jean-Robert MANOUVRIER ,  Pascal FONTENEAU ,  Xavier MONTAGNER

IPC: H01L27/146 ,  H01L29/423

CPC classification number: H01L27/14614 ,  H01L27/14607 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14641 ,  H01L27/14643 ,  H01L27/14687 ,  H01L27/14689 ,  H01L29/4236

Abstract: The present disclosure relates to a photodiode comprising: a P-conductivity type substrate region, an electric charge collecting region for collecting electric charges appearing when a rear face of the substrate region receives light, the collecting region comprising an N-conductivity type region formed deep in the substrate region, an N-conductivity type read region formed in the substrate region, and an isolated transfer gate, formed in the substrate region in a deep isolating trench extending opposite a lateral face of the N-conductivity type region, next to the read region, and arranged for receiving a gate voltage to transfer electric charges stored in the collecting region toward the read region.

Abstract translation: 本发明涉及一种光电二极管，包括：P导电型衬底区域，用于收集当衬底区域的后表面接收光时出现的电荷的电荷收集区域，所述收集区域包括形成深的N导电类型区域 在基板区域中，形成在基板区域中的N导电型读取区域和隔离的转移栅极，形成在与N导电型区域的侧面相反延伸的深隔离沟槽中的基板区域中， 并且被布置为接收栅极电压以将存储在收集区域中的电荷转移到读取区域。

公开(公告)号：US20150262908A1

公开(公告)日：2015-09-17

申请号：US14643837

申请日：2015-03-10

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Pascal Ancey ,  Simon Gousseau ,  Olga Kokshagina

IPC: H01L23/427 ,  H01L21/48 ,  F28D15/04 ,  H01L21/3065 ,  H01L21/02 ,  H01L23/367 ,  H01L23/473 ,  H01L21/3205

CPC classification number: H01L23/427 ,  F28D15/04 ,  F28D15/046 ,  F28D2015/0225 ,  H01L21/02164 ,  H01L21/30655 ,  H01L21/32051 ,  H01L21/32056 ,  H01L21/4803 ,  H01L23/367 ,  H01L23/473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a heat pipe, including the steps of: forming in a substrate a cylindrical opening provided with a plurality of ring-shaped recessed radially extending around a central axis of the opening; arranging in the recesses separate ring-shaped strips made of a material catalyzing the growth of carbon nanotubes; and growing carbon nanotubes in the opening from said ring-shaped strips.

Abstract translation: 一种制造热管的方法，包括以下步骤：在基板上形成圆柱形开口，所述圆柱形开口设置有围绕所述开口的中心轴线径向延伸的多个环状凹部; 在凹部中排列分离由催化碳纳米管生长的材料制成的环形条; 以及在所述环形条的开口中生长碳纳米管。

公开(公告)号：US20150220456A1

公开(公告)日：2015-08-06

申请号：US14610924

申请日：2015-01-30

Applicant: STMicroelectronics SA

Inventor： Bruno Fel

IPC: G06F12/14 ,  G06F12/08

CPC classification number: G06F12/1408 ,  G06F12/0802 ,  G06F21/125 ,  G06F2212/1052 ,  G06F2212/603

Abstract: Program code intended to be copied into the cache memory of a microprocessor is transferred encrypted between the random-access memory and the processor, and the decryption is carried out at the level of the cache memory. A checksum may be inserted into the cache lines in order to allow integrity verification, and this checksum is then replaced with a specific instruction before delivery of an instruction word to the central unit of the microprocessor.

Abstract translation: 旨在复制到微处理器的高速缓冲存储器中的程序代码在随机存取存储器和处理器之间被加密传送，并且在高速缓冲存储器的级别执行解密。 可以将校验和插入到高速缓存行中以便允许完整性验证，然后在将指令字发送到微处理器的中央单元之前，该校验和被替换为特定指令。

公开(公告)号：US20150206662A1

公开(公告)日：2015-07-23

申请号：US14416978

申请日：2013-07-12

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA

Inventor： Yann Lamy ,  Olivier Guiller ,  Sylvain Joblot

IPC: H01G4/30 ,  H05K1/18

CPC classification number: H01G4/306 ,  H01G4/33 ,  H01G4/38 ,  H01L28/87 ,  H01L28/91 ,  H05K1/181

Abstract: A method for producing a capacitor stack in one portion of a substrate, the method including: forming a cavity along a thickness of the portion of the substrate from an upper face of the substrate, depositing a plurality of layers contributing to the capacitor stack onto the wall of the cavity and onto the surface of the upper face, and removing matter from the layers until the surface of the upper face is reached. The forming of the cavity includes forming at least one trench and, associated with each trench, at least one box. The at least one trench includes a trench outlet that opens into the box. The box includes a box outlet that opens at the surface of the upper face, and the box outlet being shaped to be larger than the trench outlet.

Abstract translation: 一种用于在基板的一部分中制造电容器堆叠的方法，所述方法包括：从所述基板的上表面沿着所述基板的所述部分的厚度形成空腔，将有助于所述电容器堆叠的多个层沉积到所述基板上 空腔的壁和上表面上，并且从层中去除物质直到达到上表面的表面。 腔的形成包括形成至少一个沟槽，并且与每个沟槽相关联，至少一个盒子。 至少一个沟槽包括通向盒子的沟槽出口。 盒子包括在上表面开口的盒子出口，盒子出口的形状大于沟槽出口。

公开(公告)号：US20150200151A1

公开(公告)日：2015-07-16

申请号：US14590404

申请日：2015-01-06

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Sandrine LHOSTIS ,  Olga Kokshagina ,  Yann Beilliard ,  Vincent Fiori

IPC: H01L23/473 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/473 ,  H01L21/56 ,  H01L23/31 ,  H01L23/3121 ,  H01L23/3135 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/16195 ,  H01L2924/167 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/00

Abstract: A device includes a support, a three-dimensional integrated structure above the support, and a lateral encapsulation region arranged around the structure. The lateral encapsulation region includes first channels configured to make it possible to circulate a cooling fluid.

Abstract translation: 一种装置包括支撑件，支撑件上方的三维集成结构以及围绕结构设置的侧向封装区域。 横向封装区域包括被配置为使得循环冷却流体成为可能的第一通道。

公开(公告)号：US20150155319A1

公开(公告)日：2015-06-04

申请号：US14559006

申请日：2014-12-03

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Romain Girard Desprolet ,  Sandrine Lhostis ,  Salim Boutami ,  Michel Marty

IPC: H01L27/146

CPC classification number: H01L31/02162 ,  G02B5/203 ,  H01L27/14621 ,  H01L27/14629 ,  H01L27/1463 ,  H01L27/14685 ,  H01L27/14687 ,  H01L31/02165 ,  H01L31/02327

Abstract: An integrated imaging device supports front face illumination with one or more photosensitive regions formed in a substrate. A lower dielectric region is provided over the substrate, the lower dielectric region having an upper face. A metal optical filter having a metal pattern is provided on the upper face (or extending into the lower dielectric region from the upper face). An upper dielectric region is provided on top of the lower dielectric region and metal optical filter. The lower dielectric region is at least part of a pre-metal dielectric layer, and the upper dielectric region is at least part of a metallization layer.

Abstract translation: 集成成像装置支持在基板中形成的一个或多个感光区域的前面照明。 下部电介质区域设置在衬底上，下部电介质区域具有上表面。 具有金属图案的金属滤光器设置在上表面（或从上表面延伸到下介电区域中）。 在下部电介质区域和金属光学滤波器的顶部设置有上部电介质区域。 下电介质区域是预金属介电层的至少一部分，并且上电介质区域是金属化层的至少一部分。

公开(公告)号：US20150142410A1

公开(公告)日：2015-05-21

申请号：US14541627

申请日：2014-11-14

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Salim Ighilahriz ,  Florian Cacho ,  Vincent Huard

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5063 ,  G06F2217/78

Abstract: A method of circuit simulation includes: simulating, by a processing device, behavior of a heterojunction bipolar transistor device based on at least a first base-emitter voltage of the transistor to determine a first base or collector current density of the HBT device; and determining whether the application of the first base-emitter voltage to the HBT device will result in base current degradation by performing a first comparison of the first current density with a first current density limit.

Abstract translation: 一种电路仿真的方法包括：通过处理器件模拟基于晶体管的至少第一基极 - 发射极电压的异质结双极晶体管器件的行为，以确定HBT器件的第一基极或集电极电流密度; 以及通过执行所述第一电流密度与第一电流密度极限的第一比较来确定是否将所述第一基极 - 发射极电压施加到所述HBT器件将导致基极电流劣化。