公开(公告)号：US10008452B2

公开(公告)日：2018-06-26

申请号：US15469964

申请日：2017-03-27

Applicant: INTEL CORPORATION

Inventor： Qing Ma ,  Johanna M. Swan ,  Robert Starkston ,  John S. Guzek ,  Robert L. Sankman ,  Aleksandar Aleksov

IPC: H01L29/40 ,  H01L23/538 ,  H01L23/15 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L21/683

CPC classification number: H01L23/5386 ,  B32B2457/08 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/13 ,  H01L24/17 ,  H01L24/19 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L25/0655 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/08238 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/81192 ,  H01L2224/814 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/18162 ,  H01L2924/2064 ,  H01L2924/20641 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/185 ,  H05K3/4688 ,  H05K2201/017 ,  H05K2203/1469 ,  Y10T156/1057 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of the present description relate to the field of fabricating microelectronic structures. The microelectronic structures may include a glass routing structure formed separately from a trace routing structure, wherein the glass routing structure is incorporated with the trace routing substrate, either in a laminated or embedded configuration. Also disclosed are embodiments of a microelectronic package including at least one microelectronic device disposed proximate to the glass routing structure of the microelectronic substrate and coupled with the microelectronic substrate by a plurality of interconnects. Further, disclosed are embodiments of a microelectronic structure including at least one microelectronic device embedded within a microelectronic encapsulant having a glass routing structure attached to the microelectronic encapsulant and a trace routing structure formed on the glass routing structure.

公开(公告)号：US09967040B2

公开(公告)日：2018-05-08

申请号：US15676611

申请日：2017-08-14

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Sasha N. Oster ,  Feras Eid ,  Adel A. Elsherbini ,  Johanna M. Swan ,  Amit Sudhir Baxi ,  Vincent S. Mageshkumar ,  Kumar Ranganathan ,  Wen-Ling M. Huang

IPC: H04B13/00 ,  A61B5/021 ,  A61B5/11 ,  A61B5/01 ,  A61B5/00 ,  A61B5/0402 ,  A61B5/145 ,  A61N7/00 ,  A61M5/142 ,  A61N1/04 ,  H04B5/00

CPC classification number: H04B13/005 ,  A61B5/0024 ,  A61B5/01 ,  A61B5/0205 ,  A61B5/021 ,  A61B5/0402 ,  A61B5/0432 ,  A61B5/1102 ,  A61B5/1107 ,  A61B5/1121 ,  A61B5/14532 ,  A61B5/14546 ,  A61B5/4839 ,  A61B5/4869 ,  A61B5/6833 ,  A61F7/007 ,  A61M5/14248 ,  A61N1/0484 ,  A61N1/0492 ,  A61N1/3603 ,  A61N7/00 ,  H04B5/0012

Abstract: Discussed generally herein are methods and devices including or providing a patch system that can help in diagnosing a medical condition and/or provide therapy to a user. A body-area network can include a plurality of communicatively coupled patches that communicate with an intermediate device. The intermediate device can provide data representative of a biological parameter monitored by the patches to proper personnel, such as for diagnosis and/or response.

公开(公告)号：US09954309B2

公开(公告)日：2018-04-24

申请号：US15215531

申请日：2016-07-20

Applicant: Intel Corporation

Inventor： Feras Eid ,  Sasha N. Oster ,  Adel A. Elsherbini ,  Aleksandar Aleksov ,  Johanna M. Swan ,  Amit Sudhir Baxi ,  Vincent S. Mageshkumar

IPC: H01R11/30 ,  H01R13/60 ,  H01R13/62 ,  H01R13/627 ,  H01R13/631

CPC classification number: H01R13/6205 ,  H01R11/30 ,  H01R13/627 ,  H01R13/631

Abstract: Discussed generally herein are methods and devices including or providing a magnetic, detachable, conductive connector to provide an electrical and mechanical connection between parts. A device can include a first substrate, at least one electric component on or at least partially in a first surface of the first substrate, an adhesive on the first surface of the first substrate to temporarily attached the device to skin of a user, a contact pad electrically coupled to an electric component of the at least one electric component, the contact pad on or at least partially in a second surface of the substrate, the first surface opposite the second surface, and a conductive magnetic connector electrically and mechanically connected to the contact pad through a first conductive adhesive.

公开(公告)号：US09915978B2

公开(公告)日：2018-03-13

申请号：US14859894

申请日：2015-09-21

Applicant: Intel Corporation

Inventor： Nadine L. Dabby ,  Lakshman Krishnamurthy ,  Braxton Lathrop ,  Aleksandar Aleksov ,  Adel Elsherbini ,  Sasha Oster ,  Tom L. Simmons

IPC: H05K3/30 ,  G06F1/16

CPC classification number: G06F1/1633 ,  H01L23/5385 ,  H01L23/5387 ,  H01L25/105 ,  H01L2225/1017 ,  H01L2225/1047 ,  H01L2924/00

Abstract: Some forms relate to a method of making a stretchable computing system. The method includes attaching a first set of conductive traces to a stretchable member; attaching a first electronic component to the first set of conductive traces; adding a first set of flexible conductors to the stretchable member such that the first set of flexible conductors is electrically connected to the first set of conductive traces; adding stretchable material to the stretchable member such that the first set of conductive traces is surrounded by the stretchable member; forming an opening in the stretchable member that exposes the first set of conductive traces; and attaching a second set of conductive traces to the stretchable member such that the second set of conductive traces fills the opening to form a via in the stretchable member that electrically connects the first set of conductive traces with the second set of conductive traces.

公开(公告)号：US09832863B2

公开(公告)日：2017-11-28

申请号：US14866614

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Aleksandar Aleksov ,  Shawna Liff

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/22 ,  H05K3/30 ,  H05K1/03

CPC classification number: H05K1/028 ,  H05K1/0283 ,  H05K1/0393 ,  H05K1/115 ,  H05K1/118 ,  H05K1/181 ,  H05K3/22 ,  H05K3/284 ,  H05K3/301 ,  H05K3/4691 ,  H05K2201/05 ,  H05K2201/057 ,  H05K2201/09263 ,  H05K2201/095 ,  H05K2203/1316

Abstract: Some forms relate to a stretchable computing device that includes a stretchable body; a first electronic component embedded within the stretchable body; a second electronic component embedded within the stretchable body; and wherein the first electronic component and the second electronic component are connected by stretchable electrical connectors that include vias. The stretchable electrical connectors are non-planar and/or may have a partial zig-zag shape and/or a partial coil shape. In some forms, the stretchable computing device further includes a textile attached to the stretchable body.

公开(公告)号：US09786769B2

公开(公告)日：2017-10-10

申请号：US15036058

申请日：2013-12-26

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/267 ,  H01L29/423 ,  H01L51/05 ,  H01L29/24 ,  H01L29/786 ,  H01L51/00 ,  H01L29/06 ,  H01L21/8258 ,  H01L29/78

CPC classification number: H01L29/66977 ,  H01L21/8258 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/24 ,  H01L29/267 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/7391 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7869 ,  H01L51/0036 ,  H01L51/0037 ,  H01L51/0038 ,  H01L51/0078 ,  H01L51/0533 ,  H01L51/0554 ,  H01L51/0562

Abstract: Described is an apparatus forming complementary tunneling field effect transistors (TFETs) using oxide and/or organic semiconductor material. One type of TFET comprises: a substrate; a doped first region, formed above the substrate, having p-type material selected from a group consisting of Group III-V, IV-IV, and IV of a periodic table; a doped second region, formed above the substrate, having transparent oxide n-type semiconductor material; and a gate stack coupled to the doped first and second regions. Another type of TFET comprises: a substrate; a doped first region, formed above the substrate, having p-type organic semiconductor material; a doped second region, formed above the substrate, having n-type oxide semiconductor material; and a gate stack coupled to the doped source and drain regions. In another example, TFET is made using organic only semiconductor materials for active regions.

公开(公告)号：US20170188464A1

公开(公告)日：2017-06-29

申请号：US14757992

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Srinivas V. Pietambaram ,  Rahul N. Manepalli

IPC: H05K1/18 ,  H05K3/40 ,  H05K1/02 ,  H05K3/00

CPC classification number: H05K1/189 ,  H01L2224/73204 ,  H05K1/0283 ,  H05K2201/09263 ,  H05K2203/1316 ,  H05K2203/308

Abstract: A stretchable electronic assembly comprising a stretchable body, a plurality of electronic components encapsulated in the stretchable body, at least one meandering conductor connected to at least one electronic component of the plurality of electronic components, at least one hollow pocket formed in the stretchable body, the at least one meandering conductor encapsulated in the stretchable body and the at least one meandering conductor located within the at least one hollow pocket formed in the stretchable body.

公开(公告)号：US20170179103A1

公开(公告)日：2017-06-22

申请号：US15450900

申请日：2017-03-06

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Mauro Kobrinsky ,  Johanna Swan ,  Rajendra C. Dias

IPC: H01L25/00 ,  H01L23/00

Abstract: Generally discussed herein are systems and apparatuses that can include apparatuses, systems, or method for a flexible, wire bonded device. According to an example an apparatus can include (1) a first rigid circuit comprising a first plurality of bond pads proximate to a first edge of the first rigid circuit, (2) a second rigid circuit comprising a second plurality of bond pads proximate to a first edge of the second rigid circuit, the second rigid circuit adjacent the first rigid circuit and the first edge of the second rigid circuit facing the first edge of the first rigid circuit, or (3) a first plurality of wire bonded wires, each wire bonded wire of the first plurality of wire bonded wires electrically and mechanically connected to a bond pad of the first plurality of bond pads and a bond pad of the second plurality of bond pads.

公开(公告)号：US09642248B2

公开(公告)日：2017-05-02

申请号：US14618235

申请日：2015-02-10

Applicant: Intel Corporation

Inventor： Qing Ma ,  Johanna M. Swan ,  Robert Starkston ,  John S. Guzek ,  Robert L. Sankman ,  Aleksandar Aleksov

IPC: H05K1/00 ,  H05K1/03 ,  H01L23/15 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H05K1/18 ,  H05K3/46 ,  H01L21/56 ,  H01L21/48 ,  H05K1/02 ,  H05K1/11

CPC classification number: H01L23/5386 ,  B32B2457/08 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/13 ,  H01L24/17 ,  H01L24/19 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L25/0655 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/08238 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/81192 ,  H01L2224/814 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/18162 ,  H01L2924/2064 ,  H01L2924/20641 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/185 ,  H05K3/4688 ,  H05K2201/017 ,  H05K2203/1469 ,  Y10T156/1057 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of the present description relate to the field of fabricating microelectronic structures. The microelectronic structures may include a glass routing structure formed separately from a trace routing structure, wherein the glass routing structure is incorporated with the trace routing substrate, either in a laminated or embedded configuration. Also disclosed are embodiments of a microelectronic package including at least one microelectronic device disposed proximate to the glass routing structure of the microelectronic substrate and coupled with the microelectronic substrate by a plurality of interconnects. Further, disclosed are embodiments of a microelectronic structure including at least one microelectronic device embedded within a microelectronic encapsulant having a glass routing structure attached to the microelectronic encapsulant and a trace routing structure formed on the glass routing structure.

公开(公告)号：US09564412B2

公开(公告)日：2017-02-07

申请号：US14961624

申请日：2015-12-07

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Sanka Ganesan

IPC: H05K7/10 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L24/14 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/1132 ,  H01L2224/11332 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/141 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: The present description relates to the field of fabricating microelectronic assemblies, wherein a microelectronic device may be attached to a microelectronic substrate with a plurality of shaped and oriented solder joints. The shaped and oriented solder joints may be substantially oval, wherein the major axis of the substantially oval solder joints may be substantially oriented toward a neutral point or center of the microelectronic device. Embodiments of the shaped and oriented solder joint may reduce the potential of solder joint failure due to stresses, such as from thermal expansion stresses between the microelectronic device and the microelectronic substrate.

Abstract translation: 本说明书涉及制造微电子组件的领域，其中微电子器件可以附接到具有多个成形和取向的焊点的微电子衬底。 成形和定向的焊接接头可以是基本上椭圆形的，其中基本上椭圆形焊点的长轴可以基本上朝向微电子器件的中性点或中心定向。 成形和取向的焊接接头的实施例可以减少由于应力（例如来自微电子器件和微电子衬底之间的热膨胀应力）引起的焊点故障的可能性。