公开(公告)号：US09337992B2

公开(公告)日：2016-05-10

申请号：US14574253

申请日：2014-12-17

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Thomas H. Greer, III ,  Jade M. Kizer ,  Brian S. Leibowitz ,  Mark A. Horowitz

IPC: H04L7/00 ,  H03L7/07 ,  H03L7/093 ,  H04L7/033

CPC classification number: H04L7/0012 ,  H03L7/07 ,  H03L7/0807 ,  H03L7/0814 ,  H03L7/091 ,  H03L7/093 ,  H04L7/0008 ,  H04L7/0331 ,  H04L7/0337

Abstract: A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal according to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock.

Abstract translation: 一种用于执行时钟和数据恢复的系统和方法。 根据数据发送器时钟的频率和接收机时钟的频率之间的偏移的变化率的至少三个估计，系统设置恢复的时钟信号的相位。

公开(公告)号：US09337872B2

公开(公告)日：2016-05-10

申请号：US14112935

申请日：2012-03-10

Applicant: Richard E. Perego

Inventor： Richard E. Perego

IPC: H03M13/35 ,  G06F11/10 ,  G06F11/16

CPC classification number: H03M13/356 ,  G06F11/10 ,  G06F11/1666

Abstract: Configurable, error-tolerant communication of memory control information between components of a memory system. A controller component and memory component each have a variable-width command/address (CA) interface that operates in conjunction with an error detection/correction (EDC) channel to enable a variable level of error detection and correction with respect to command/address information conveyed between the two components as the widths of the CA interfaces are adjusted.

Abstract translation: 存储器系统的组件之间的可配置的，容错的通信存储器控制信息。 控制器组件和存储器组件各自具有与错误检测/校正（EDC）通道一起操作的可变宽度命令/地址（CA）接口，以实现关于命令/地址信息的可变级别的错误检测和校正 由于CA接口的宽度被调整，在两个部件之间传送。

公开(公告)号：US09330735B2

公开(公告)日：2016-05-03

申请号：US13640084

申请日：2012-06-08

Applicant: James Edward Harris ,  Thomas Vogelsang ,  Frederick A. Ware ,  Ian P. Shaeffer

Inventor： James Edward Harris ,  Thomas Vogelsang ,  Frederick A. Ware ,  Ian P. Shaeffer

IPC: G11C7/00 ,  G11C7/06 ,  G11C5/02 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/08

CPC classification number: G11C7/1039 ,  G11C5/025 ,  G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/222 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the sub-row to be activated.

Abstract translation: 存储器组件内的行激活操作相对于子行执行，而不是完整的存储行，以减少功耗。 此外，除了响应于行命令激活子代以外，子代激活操作被延迟，直到接收到指定要执行的列操作的列命令和要被激活的子行。

公开(公告)号：US09306568B2

公开(公告)日：2016-04-05

申请号：US14728917

申请日：2015-06-02

Applicant: Rambus Inc.

Inventor： Kyung Suk Oh ,  Ian P. Shaeffer

IPC: H03K17/16 ,  H03K19/00 ,  G06F13/40 ,  G11C11/4093 ,  H03K19/0175 ,  G11C11/401 ,  G11C11/419 ,  G11C16/26 ,  G11C11/41 ,  G11C11/4063 ,  G11C11/413 ,  G11C11/417 ,  G11C16/06 ,  G11C16/32

CPC classification number: H03K19/0005 ,  G06F3/0605 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/4086 ,  G11C11/401 ,  G11C11/4063 ,  G11C11/4093 ,  G11C11/41 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C16/06 ,  G11C16/26 ,  G11C16/32 ,  H03K19/017545

Abstract: A memory controller transmits a plurality of control values to a non-volatile memory device together with one or more programming commands. The plurality of control values include (i) a first control value that specifies a first termination resistance to be applied to an I/O node of the non-volatile memory device during an interval in which a first data signal transmitted on a bidirectional signaling line coupled to the I/O node is to be received within the non-volatile memory device and (ii) a second control value that specifies a second termination resistance to be applied to the I/O node during an interval in which a second data signal is transmitted on the bidirectional signaling line by another non-volatile memory device.

Abstract translation: 存储器控制器与一个或多个编程命令一起将多个控制值发送到非易失性存储器件。 多个控制值包括：（i）第一控制值，其指定在双向信令线路中发送的第一数据信号的间隔期间应用于非易失性存储器件的I / O节点的第一终端电阻 耦合到所述I / O节点的所述I / O节点将被接收在所述非易失性存储器设备内;以及（ii）第二控制值，其指定在所述I / O节点期间施加的第二终端电阻， 在双向信令线路上由另一非易失性存储器件发送。

公开(公告)号：US09305644B2

公开(公告)日：2016-04-05

申请号：US14125913

申请日：2012-06-22

Applicant: Mark D. Kellam ,  Gary Bela Bronner

Inventor： Mark D. Kellam ,  Gary Bela Bronner

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C13/004 ,  G11C13/00 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0052 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2418 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/143

Abstract: A resistance memory includes a resistance memory cell having a resistance memory element and a two-terminal access device in series. The two-terminal access device affects the current-voltage characteristic of the resistance memory cell. The resistance memory additionally includes a circuit to apply across the resistance memory cell a set pulse having a set polarity to set the resistance memory cell to a low-resistance state that is retained after application of the set pulse, a reset pulse having a reset polarity, opposite to the set polarity, to reset the resistance memory cell to a high-resistance state that is retained after application of the reset pulse, and a read pulse of the reset polarity and smaller in magnitude than the reset pulse to determine the resistance state of the resistance memory cell without changing the resistance state of the resistance memory cell.

Abstract translation: 电阻存储器包括具有电阻存储元件和串联的两端存取装置的电阻存储单元。 双端子存取装置影响电阻存储单元的电流 - 电压特性。 电阻存储器还包括电路，跨越电阻存储单元施加具有设定极性的设定脉冲，以将电阻存储单元设置为在施加设置脉冲之后保持的低电阻状态，具有复位极性的复位脉冲 与设定的极性相反，将电阻存储单元复位到施加复位脉冲之后保持的高电阻状态，以及复位极性的读取脉冲和幅度比复位脉冲更小以确定电阻状态 的电阻存储单元，而不改变电阻存储单元的电阻状态。

公开(公告)号：US09298228B1

公开(公告)日：2016-03-29

申请号：US14810410

申请日：2015-07-27

Applicant: Rambus Inc.

Inventor： Abhijit M. Abhyankar ,  Ravindranath Kollipara ,  Thomas J. Giovannini ,  Ming Li ,  David A. Secker ,  Arun Vaidyanath ,  Donald R. Mullen ,  Adrian F. Torres

IPC: H05K1/11 ,  H05K1/14 ,  G06F1/18

CPC classification number: G06F1/185

Abstract: A computing system having a memory riser sub-system. The computing system includes a motherboard with a memory module connector and a riser card inserted into the first memory module connector. A first mezzanine card is connected to the riser card. The first mezzanine card includes a first mezzanine memory module connector for a first memory module and a second mezzanine memory module connector for a second memory module. A memory channel electrically connects the memory controller to the first mezzanine memory module connector and the second mezzanine module connector via the motherboard, the first riser card and the first mezzanine card. The memory channel may be divided into a first data sub-channel connected to the first mezzanine memory module connector and a second data sub-channel connected to the second mezzanine memory module connector.

Abstract translation: 具有存储器提升子子系统的计算系统。 计算系统包括具有存储器模块连接器的主板和插入到第一存储器模块连接器中的转接卡。 第一个夹层卡连接到转接卡。 第一夹层卡包括用于第一存储器模块的第一夹层存储器模块连接器和用于第二存储器模块的第二夹层存储器模块连接器。 存储通道经由主板，第一转接卡和第一夹层卡将存储器控制器电连接到第一夹层存储器模块连接器和第二夹层模块连接器。 存储器通道可以被分成连接到第一夹层存储器模块连接器的第一数据子通道和连接到第二夹层存储器模块连接器的第二数据子通道。

公开(公告)号：US09287880B2

公开(公告)日：2016-03-15

申请号：US13988615

申请日：2011-11-10

Applicant: Marko Aleksic ,  Brian S. Leibowitz

Inventor： Marko Aleksic ,  Brian S. Leibowitz

IPC: H03L7/24 ,  H03L1/00 ,  H03K3/03 ,  H03L7/083

CPC classification number: H03L1/00 ,  H03K3/0315 ,  H03L7/083 ,  H03L7/24

Abstract: A variable injection-strength injection-locked oscillator (ILO) is described. The variable injection-strength ILO can output an output clock signal based on an input clock signal. The variable injection-strength ILO can pause, restart, slow down, or speed up the output clock signal synchronously with respect to the input clock signal in response to receiving power mode information. Specifically, the variable injection-strength ILO can be operated under relatively strong injection when the input clock signal is paused, restarted, slowed down, or sped up.

Abstract translation: 描述了可变注射强度注射锁定振荡器（ILO）。 可变注入强度ILO可以基于输入时钟信号输出输出时钟信号。 响应于接收功率模式信息，可变注入强度ILO可以相对于输入时钟信号同步地暂停，重新启动，减慢或加速输出时钟信号。 具体地说，当输入时钟信号被暂停，重新启动，减速或加速时，可变注入强度ILO可以在相对强的注入下操作。

公开(公告)号：US09287239B2

公开(公告)日：2016-03-15

申请号：US13641680

申请日：2011-04-13

Applicant: Frederick A. Ware ,  Ely Tsern ,  Thomas Vogelsang

Inventor： Frederick A. Ware ,  Ely Tsern ,  Thomas Vogelsang

IPC: H01L25/16 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H01L23/48

CPC classification number: H01L23/481 ,  G06F3/0604 ,  G06F3/0629 ,  G06F3/0673 ,  G06F2213/0038 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2225/06544 ,  H01L2924/014

Abstract: An integrated circuit die includes conductive connection sites located at least on a surface of the integrated circuit die within a contiguous region thereof. The integrated circuit also includes a core circuit located outside the contiguous region. The core circuit is coupled to at least one of the connection sites.

Abstract translation: 集成电路管芯包括至少位于其连续区域内的集成电路管芯的表面上的导电连接位置。 集成电路还包括位于连续区域外的核心电路。 核心电路耦合到至少一个连接位置。

公开(公告)号：US09275733B2

公开(公告)日：2016-03-01

申请号：US14693759

申请日：2015-04-22

Applicant: Rambus Inc.

Inventor： Richard E. Perego ,  Pradeep Batra ,  Steven Woo ,  Lawrence Lai ,  Chi-Ming Yeung

IPC: G06F5/00 ,  G11C14/00 ,  G06F12/02 ,  G06F12/10 ,  G06F13/38 ,  G06F12/06 ,  G11C7/10 ,  G06F12/00 ,  G06F13/42

CPC classification number: G06F3/061 ,  G06F3/0629 ,  G06F3/0685 ,  G06F12/00 ,  G06F12/0246 ,  G06F12/0638 ,  G06F12/10 ,  G06F13/385 ,  G06F13/4239 ,  G06F2212/2022 ,  G06F2212/205 ,  G06F2212/251 ,  G06F2212/7201 ,  G06F2212/7206 ,  G11C7/1072 ,  G11C14/0018 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.

公开(公告)号：US09269460B2

公开(公告)日：2016-02-23

申请号：US14840989

申请日：2015-08-31

Applicant: RAMBUS INC.

Inventor： Adrian E. Ong ,  Fan Ho

IPC: G11C29/00 ,  G11C29/04

CPC classification number: G11C29/76 ,  G11C11/401 ,  G11C11/4085 ,  G11C29/027 ,  G11C29/04 ,  G11C29/12 ,  G11C29/4401 ,  G11C29/48 ,  G11C29/78 ,  G11C29/789 ,  G11C29/802 ,  G11C2229/743

Abstract: A controller includes a memory test logic circuit to detect a malfunctioning row of primary data storage elements within an external memory device, an internal memory to store an address corresponding to the malfunctioning row of the external memory device, and a memory setup logic circuit to initiate a repair mode in the external memory device and to end the repair mode in the external memory device. The controller further includes a port to couple to an address line to transmit the address corresponding to the malfunctioning row of the external memory device.

Abstract translation: 控制器包括：存储器测试逻辑电路，用于检测外部存储器件内主要数据存储元件的故障行;存储与外部存储器件故障行对应的地址的内部存储器;以及存储器设置逻辑电路，以启动 外部存储器件中的修复模式，并结束外部存储器件中的修复模式。 控制器还包括耦合到地址线以传送对应于外部存储器件的故障行的地址的端口。