公开(公告)号：US20090212414A1

公开(公告)日：2009-08-27

申请号：US12431956

申请日：2009-04-29

申请人： Jong-Joo LEE

发明人： Jong-Joo LEE

IPC分类号： H01L23/52

CPC分类号： H01L23/5286 ,  H01L21/84 ,  H01L27/10894 ,  H01L27/1203 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2224/05552

摘要： Provided are embodiments of semiconductor chips having a redistributed metal interconnection directly connected to power/ground lines of an internal circuit are provided. Embodiments of the semiconductor chips include an internal circuit formed on a semiconductor substrate. A chip pad is disposed on the semiconductor substrate. The chip pad is electrically connected to the internal circuit through an internal interconnection. A passivation layer is provided over the chip pad. A redistributed metal interconnection is provided on the passivation layer. The redistributed metal interconnection directly connects the internal interconnection to the chip pad through a via-hole and a chip pad opening, which penetrate at least the passivation layer. Methods of fabricating the semiconductor chip are also provided.

摘要翻译： 提供了具有直接连接到内部电路的电源/接地线的重分布金属互连的半导体芯片的实施例。 半导体芯片的实施例包括形成在半导体衬底上的内部电路。 芯片焊盘设置在半导体衬底上。 芯片焊盘通过内部互连电连接到内部电路。 钝化层设置在芯片焊盘的上方。 在钝化层上设置重新分布的金属互连。 再分布的金属互连通过穿孔至少钝化层的通孔和芯片焊盘开口将内部互连直接连接到芯片焊盘。 还提供了制造半导体芯片的方法。

公开(公告)号：US20090065950A1

公开(公告)日：2009-03-12

申请号：US12267343

申请日：2008-11-07

申请人： Jong-Joo LEE ,  Dong-Ho LEE

发明人： Jong-Joo LEE ,  Dong-Ho LEE

IPC分类号： H01L23/52

CPC分类号： H01L25/0657 ,  H01L23/13 ,  H01L23/66 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Provided are a stack chip and a stack chip package having the stack chip. Internal circuits of two semiconductor chips are electrically connected to each other through an input/output buffer connected to an external connection terminal. The semiconductor chip has chip pads, input/output buffers and internal circuits connected through circuit wirings. The semiconductor chip also has connection pads connected to the circuit wirings connecting the input/output buffers to the internal circuits. The semiconductor chips include a first chip and a second chip. The connection pads of the first chip are electrically connected to the connection pads of the second chip through electrical connection means. Input signals input through the external connection terminals are input to the internal circuits of the first chip or the second chip via the chip pads and the input/output buffers of the first chip, and the connection pads of the first chip and the second chip.

摘要翻译： 提供了具有堆叠芯片的堆叠芯片和堆叠芯片封装。 两个半导体芯片的内部电路通过连接到外部连接端子的输入/输出缓冲器彼此电连接。 半导体芯片具有芯片焊盘，输入/输出缓冲器和通过电路布线连接的内部电路。 半导体芯片还具有连接到将输入/输出缓冲器连接到内部电路的电路布线的连接焊盘。 半导体芯片包括第一芯片和第二芯片。 第一芯片的连接焊盘通过电连接装置电连接到第二芯片的连接焊盘。 通过外部连接端子输入的输入信号经由芯片焊盘和第一芯片的输入/输出缓冲器以及第一芯片和第二芯片的连接焊盘输入到第一芯片或第二芯片的内部电路。

公开(公告)号：US20050269684A1

公开(公告)日：2005-12-08

申请号：US11137803

申请日：2005-05-26

申请人： Seung-Duk Baek ,  Dong-Hyeon Jang ,  Jong-Joo Lee

发明人： Seung-Duk Baek ,  Dong-Hyeon Jang ,  Jong-Joo Lee

IPC分类号： H01L21/768 ,  H01L21/44 ,  H01L23/31 ,  H01L23/48 ,  H01L23/485 ,  H01L23/50 ,  H01L23/525

CPC分类号： H01L24/10 ,  H01L21/76802 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A semiconductor device package includes a substrate, first and second chip pads spaced apart over a surface of the substrate, and an insulating layer located over the surface of the substrate. The insulating layer includes a stepped upper surface defined by at least a lower reference potential line support surface portion, and an upper signal line support surface portion, where a thickness of the insulating layer at the lower reference potential line support surface portion is less than a thickness of the insulating layer at the upper signal line support surface portion. The package further includes a conductive reference potential line electrically connected to the first chip pad and located on the lower reference potential support surface portion of the insulating layer, a conductive signal line electrically connected to the second chip pad and located on the upper signal line support surface portion, and first and second external terminals electrically connected to the conductive reference potential line and the conductive signal line, respectively.

摘要翻译： 半导体器件封装包括衬底，在衬底的表面上间隔开的第一和第二芯片焊盘以及位于衬底表面上的绝缘层。 绝缘层包括由至少一个下参考电位线支撑表面部分限定的阶梯状上表面和上信号线支撑表面部分，其中下参考电位线支撑表面部分处的绝缘层的厚度小于 上部信号线支撑表面部分处的绝缘层的厚度。 所述封装还包括电连接到所述第一芯片焊盘并且位于所述绝缘层的下参考电位支撑表面部分上的导电参考电位线，电连接到所述第二芯片焊盘并位于所述上信号线支撑件上的导电信号线 表面部分以及分别电连接到导电参考电位线和导电信号线的第一和第二外部端子。

公开(公告)号：US20050199993A1

公开(公告)日：2005-09-15

申请号：US11065822

申请日：2005-02-24

申请人： Jong-Joo Lee ,  Young-Hee Song

发明人： Jong-Joo Lee ,  Young-Hee Song

IPC分类号： H01L23/36 ,  H01L23/02

CPC分类号： H01L23/3157 ,  H01L23/13 ,  H01L23/552 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/05026 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/15151 ,  H01L2924/15331 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： A semiconductor package which can be stacked to form a package stack that includes a semiconductor chip with bonding pads, a board having contact pads on its upper surface and bump pads on its lower surface, a heat spreader attached to the rear side of the semiconductor chip and covering the upper surface of the board, and external contact terminals including ground terminals and signal terminals formed on the bump pads. The contact pads of the board include ground contact pads connected with the ground terminals and signal contact pads connected with the signal terminals. The heat spreader includes indented parts to expose the signal contact pads and protruded parts to cover the ground contact pads which are exposed through holes formed on the protruded parts on the peripheral part of the heat spreader. The semiconductor package can alternatively have the heat spreader attached to the lower surface of the board.

摘要翻译： 一种半导体封装，其可堆叠形成包括具有接合焊盘的半导体芯片的封装堆叠，在其上表面上具有接触焊盘的板和其下表面上的凸块焊盘;附接到半导体芯片的后侧的散热器 并覆盖电路板的上表面，以及包括接地端子和形成在凸块上的信号端子的外部接触端子。 板的接触垫包括与接地端子连接的接地焊盘和与信号端子连接的信号接触焊盘。 散热器包括凹陷部分，以暴露信号接触焊盘和突出部分，以覆盖通过形成在散热器的周边部分上的突出部分上的孔暴露的接地焊盘。 半导体封装也可以具有附着到板的下表面的散热器。

公开(公告)号：US20050104184A1

公开(公告)日：2005-05-19

申请号：US10983576

申请日：2004-11-09

申请人： Mee-Hyun Ahn ,  Jong-Joo Lee

发明人： Mee-Hyun Ahn ,  Jong-Joo Lee

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/607 ,  H01L21/82 ,  H01L21/822 ,  H01L23/48 ,  H01L23/50 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L27/04 ,  H01L23/02

CPC分类号： H01L24/85 ,  H01L23/50 ,  H01L24/06 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A unit semiconductor chip package may includes a semiconductor chip, a first series of bonding pads in a first area, a second series of bonding pads in a second area, a plurality of bonding fingers provided on a substrate and a plurality of bonding wires. Each of the first series of bonding pads may be electrically connected to a corresponding one of the plurality of bonding fingers by one bonding wire and each of the second series of bonding pad may be electrically connected to one of the plurality of bonding fingers by at least two bonding wires or the plurality of bonding wires electrically connecting the first series of bonding pads may be longer and the plurality of bonding wires electrically connecting the second series of bonding pads may be longer or shorter.

摘要翻译： 单元半导体芯片封装可以包括半导体芯片，第一区域中的第一系列接合焊盘，第二区域中的第二系列焊盘，设置在基板上的多个接合指状物和多个接合线。 第一系列接合焊盘中的每一个可以通过一个接合线电连接到多个接合指的相应一个，并且第二系列接合焊盘中的每一个可以至少电连接到多个接合指中的一个 电连接第一系列接合焊盘的两个接合线或多个接合线可以更长，并且电连接第二接合焊盘的多个接合线可以更长或更短。

公开(公告)号：US20050040508A1

公开(公告)日：2005-02-24

申请号：US10798943

申请日：2004-03-12

申请人： Jong-Joo Lee

发明人： Jong-Joo Lee

IPC分类号： H01L23/12 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10 ,  H01L21/48 ,  H01L23/52

CPC分类号： H01L23/4985 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49833 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A package stack has at least two packages of area array types (AAT), each having connecting pads. A flexible cable having conductive patterns is provided between the AAT packages and electrically connected to the connecting pads of the packages.

摘要翻译： 封装堆栈具有至少两个区域阵列类型（AAT）封装，每个封装具有连接焊盘。 具有导电图案的柔性电缆设置在AAT封装之间并电连接到封装的连接焊盘。

公开(公告)号：US10128191B2

公开(公告)日：2018-11-13

申请号：US15620301

申请日：2017-06-12

申请人： Jong-joo Lee

发明人： Jong-joo Lee

IPC分类号： H05K7/00 ,  H01L23/538 ,  H01L23/498 ,  H01L25/10 ,  H01L23/00

摘要： A package-on-package (PoP)-type package includes a first semiconductor package having a first passive element and a first semiconductor device mounted on a first substrate, and a second semiconductor package having a second semiconductor device mounted on a second substrate. The first passive element is electrically connected to the second semiconductor device. Related devices are also discussed.

公开(公告)号：US09391048B2

公开(公告)日：2016-07-12

申请号：US14201756

申请日：2014-03-07

申请人： Jong-joo Lee

发明人： Jong-joo Lee

IPC分类号： H01L23/02 ,  H01L25/065 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/9202 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor package, comprising: a substrate; a first semiconductor chip; and at least one second semiconductor chip. The first semiconductor chip and the at least one second semiconductor chip are stacked on the substrate; the first semiconductor chip is electrically connected with the substrate; and an electrical connection of each second semiconductor chip is formed through a secondary input/output buffer of the first semiconductor chip.

摘要翻译： 一种半导体封装，包括：衬底; 第一半导体芯片; 和至少一个第二半导体芯片。 第一半导体芯片和至少一个第二半导体芯片堆叠在基板上; 第一半导体芯片与衬底电连接; 并且通过第一半导体芯片的次级输入/输出缓冲器形成每个第二半导体芯片的电连接。

公开(公告)号：US08604616B2

公开(公告)日：2013-12-10

申请号：US13357743

申请日：2012-01-25

申请人： Jong-Joo Lee

发明人： Jong-Joo Lee

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/525 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/12 ,  H01L24/16 ,  H01L24/48 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/06136 ,  H01L2224/13009 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2518 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/4824 ,  H01L2224/83851 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/29075 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor chip including a chip via plug penetrating a substrate, a semiconductor stack thereof, a semiconductor device package thereof, and an electronic apparatus having the same are disclosed. The semiconductor chip comprising, a substrate including an inner semiconductor circuit, a conductive redistribution structure formed on the substrate including a conductive redistribution interconnection and a conductive redistribution via plug, wherein the redistribution via plug is connected to the inner semiconductor circuit; a conductive chip pad formed on the substrate, and a conductive chip via plug configured to penetrate the substrate and electrically connected to the redistribution structure.

摘要翻译： 公开了一种半导体芯片，其包括穿过基板的芯片通孔插塞，其半导体叠层，其半导体器件封装以及具有该半导体芯片的电子设备。 所述半导体芯片包括：包括内部半导体电路的基板，形成在所述基板上的导电再分布结构，所述导电再分布结构包括导电再分配互连和通过插头的导电再分布，其中所述再分配经由插头连接到所述内部半导体电路; 形成在所述基板上的导电芯片焊盘，以及被配置为穿透所述基板并电连接到所述再分布结构的导电芯片通孔插头。

公开(公告)号：US08319351B2

公开(公告)日：2012-11-27

申请号：US12689717

申请日：2010-01-19

申请人： Jong-Joo Lee

发明人： Jong-Joo Lee

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L25/18 ,  H01L23/481 ,  H01L24/02 ,  H01L24/12 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Provided are a planar multi semiconductor chip package in which a processor and a memory device are connected to each other via a through electrode and a method of manufacturing the planar multi semiconductor chip package. The planar multi semiconductor chip package includes: a substrate comprising a plurality of first circuit patterns on a first surface and a plurality of second circuit patterns on a second surface; a first semiconductor chip comprising a plurality of memory devices arranged on the substrate, wherein first memory devices surround at least a portion of second memory devices; a second semiconductor chip stacked on the first semiconductor chip and corresponding to the second memory devices; and a plurality of through electrodes arranged on the second memory devices and connecting the first and second semiconductor chips to the second circuit pattern of the substrate.

摘要翻译： 提供一种平面多半导体芯片封装，其中处理器和存储器件经由通孔彼此连接，以及制造平面多芯片封装的方法。 平面多晶半导体芯片封装包括：在第一表面上包括多个第一电路图案的基板和在第二表面上的多个第二电路图案; 包括布置在所述基板上的多个存储器件的第一半导体芯片，其中第一存储器件围绕第二存储器件的至少一部分; 堆叠在第一半导体芯片上并对应于第二存储器件的第二半导体芯片; 以及布置在第二存储器件上并将第一和第二半导体芯片连接到基板的第二电路图案的多个贯通电极。