公开(公告)号：US20090173522A1

公开(公告)日：2009-07-09

申请号：US12345349

申请日：2008-12-29

申请人： Hajime Sakamoto ,  Shuichi Kawano ,  Daiki Komatsu ,  Toshiki Furutani ,  Hiroshi Segawa

发明人： Hajime Sakamoto ,  Shuichi Kawano ,  Daiki Komatsu ,  Toshiki Furutani ,  Hiroshi Segawa

IPC分类号： H05K1/02 ,  H05K13/00

CPC分类号： H01L23/5386 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/5383 ,  H01L23/5384 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15192 ,  H01L2924/3011 ,  Y10T29/49155

摘要： An interposer having a support substrate, a first insulation layer made of an inorganic material and formed over the support substrate, and a second insulation layer formed over the first insulation layer. The first insulation layer has a first land, a second land and a first wiring electrically connecting the first land and the second land. The second insulation layer has a first pad positioned to load a first electronic component, a second pad positioned to load a second electronic component, a second wiring electrically connected to the second pad, a first via conductor electrically connecting the first land and the first pad, and a second via conductor electrically connecting the second land and the second wiring. The first wiring and second wiring electrically connect the first pad and the second pad, and the second wiring has a lower wiring resistance per unit length than the first wiring.

摘要翻译： 具有支撑衬底的中介层，由无机材料制成并形成在支撑衬底上的第一绝缘层，以及形成在第一绝缘层上的第二绝缘层。 第一绝缘层具有第一焊盘，第二焊盘和电连接第一焊盘和第二焊盘的第一布线。 所述第二绝缘层具有第一焊盘，所述第一焊盘定位成装载第一电子部件，第二焊盘定位成装载第二电子部件，电连接到所述第二焊盘的第二焊盘，将所述第一焊盘和所述第一焊盘电连接的第一通孔导体 以及电连接第二焊盘和第二布线的第二通孔导体。 第一布线和第二布线将第一焊盘和第二焊盘电连接，并且第二布线具有比第一布线更低的每单位长度的布线电阻。

公开(公告)号：US20090053911A1

公开(公告)日：2009-02-26

申请号：US12254608

申请日：2008-10-20

申请人： Takashi KARIYA ,  Toshiki Furutani ,  Takeshi Kawanishi

发明人： Takashi KARIYA ,  Toshiki Furutani ,  Takeshi Kawanishi

IPC分类号： H01R12/02

CPC分类号： H05K3/4015 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/45 ,  H01L24/72 ,  H01L24/78 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/451 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/78301 ,  H01L2224/786 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/838 ,  H01L2224/851 ,  H01L2224/85205 ,  H01L2224/90 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3011 ,  H05K3/326 ,  H05K3/341 ,  H05K2201/10265 ,  H05K2201/10287 ,  H05K2203/049 ,  Y10T29/49135 ,  Y10T29/49142 ,  Y10T29/49149 ,  Y10T29/49153 ,  H01L2224/13099 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2224/48 ,  H01L2924/00015 ,  H01L2224/05599

摘要： A printed circuit board according to the present invention is a printed circuit board (4) including a component mounting pin (1) made of a metal wire to connect with a semiconductor chip (10). The semiconductor chip (10) is a surface mounting type semiconductor chip having an electrode pad on its mounting surface for use in a flip-chip mounting system. The component mounting pin (1) is formed by using wire-bonding technology. This printed circuit board (4) is able to decrease malconnections or disconnection caused by a difference between the coefficients of thermal expansion of the semiconductor chip (10) and the printed circuit board (4).

公开(公告)号：US07495332B2

公开(公告)日：2009-02-24

申请号：US11563355

申请日：2006-11-27

申请人： Takashi Kariya ,  Toshiki Furutani ,  Hirofumi Goto ,  Shin-ichiro Iwanaga

发明人： Takashi Kariya ,  Toshiki Furutani ,  Hirofumi Goto ,  Shin-ichiro Iwanaga

IPC分类号： H01L23/14 ,  H01L23/28

CPC分类号： H01L23/49822 ,  H01L23/49811 ,  H01L23/49816 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/0271 ,  H05K1/0373 ,  H05K1/115 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/068 ,  H05K2201/10674

摘要： A multilayer printed wiring board is equipped with a core board 20, a build-up layer 30 formed on the core board 20 so as to have a conductor pattern 32 on the upper surface thereof, a low-elasticity layer 40 formed on the build-up layer 30, lands 52 that are provided on the upper surface of the low-elasticity layer 40 and connected to an IC chip 70 via solder bumps 66, and conductor posts 50 that penetrate through the low-elasticity layer 40 and electrically connect the lands 52 to the conductor pattern 32. The low-elasticity layer 40 is formed of resin composition containing epoxy resin, phenol resin, cross-linked rubber particles and a hardening catalyst.

摘要翻译： 多层印刷电路板配备有芯板20，形成在芯板20上的积层30，以在其上表面具有导体图案32，形成在构建层20上的低弹性层40， 上层30，设置在低弹性层40的上表面上并通过焊锡凸块66连接到IC芯片70的焊盘52以及穿过低弹性层40并导电连接焊盘的导体柱50 低弹性层40由包含环氧树脂，酚醛树脂，交联橡胶颗粒和硬化催化剂的树脂组合物形成。

公开(公告)号：US07489521B2

公开(公告)日：2009-02-10

申请号：US11778989

申请日：2007-07-17

申请人： Takashi Kariya ,  Toshiki Furutani

发明人： Takashi Kariya ,  Toshiki Furutani

IPC分类号： H05K1/11 ,  H05K1/14

CPC分类号： H05K1/0271 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/0373 ,  H05K1/115 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/068 ,  H05K2201/10674 ,  Y10T29/49126 ,  Y10T29/49151 ,  Y10T29/49162 ,  H01L2224/0401

摘要： A multilayer printed wiring board (10) includes: a build-up layer (30) that is formed on a core substrate (20) and has a conductor pattern (32) disposed on an upper surface; a low elastic modulus layer (40) that is formed on the build-up layer (30); lands (52) that are disposed on an upper surface of the low elastic modulus layer (40) and connected via solder bumps (66) to a IC chip (70); and conductor posts (50) that pass through the low elastic modulus layer (40) and electrically connect lands (52) with conductor patterns (32). The conductor posts (50) have the aspect ratio Rasp (height/minimum diameter) of not less than 4 and the minimum diameter exceeding 30 μm, and the aspect ratio Rasp of external conductor posts 50a, which are positioned at external portions of the low elastic modulus layer (40), is greater than or equal to the aspect ratio Rasp of internal conductor posts (50b), which are positioned at internal portions of the low elastic modulus layer (40).

摘要翻译： 多层印刷布线板（10）包括：形成在芯基板（20）上并具有布置在上表面上的导体图案（32）的堆积层（30） 形成在积层（30）上的低弹性模量层（40）; 设置在低弹性模量层（40）的上表面并通过焊锡凸块（66）连接到IC芯片（70）的平台（52）; 以及穿过低弹性模量层（40）并将焊盘（52）与导体图案（32）电连接的导体柱（50）。 导体柱50具有不小于4的纵横比Rasp（高度/最小直径）和最小直径超过30μm，并且外部导体柱50a的纵横比Rasp位于低的外部 弹性模量层（40）大于或等于位于低弹性模量层（40）的内部的内部导体柱（50b）的纵横比Rasp。

公开(公告)号：US07462784B2

公开(公告)日：2008-12-09

申请号：US11415117

申请日：2006-05-02

申请人： Takashi Kariya ,  Toshiki Furutani ,  Takeshi Kawanishi

发明人： Takashi Kariya ,  Toshiki Furutani ,  Takeshi Kawanishi

IPC分类号： H05K1/16

CPC分类号： H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/112 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/10674 ,  H01L2224/05599

摘要： This invention provides a multilayer printed wiring board which achieves fine pitches. A heat resistant substrate is incorporated in a multilayer printed wiring board and interlayer resin insulation layer and conductive layer are placed alternately on the heat resistant substrate. A built-up wiring board in which respective conductive layers are connected by via hole is formed. A via hole is formed on the surface of a mirror-processed Si substrate by using a heat resistant substrate composed of Si substrate so that finer wiring than a resin substrate having unevenness in its surface can be formed, whereby achieving fine pitches. Further, by forming the wiring on a mirror processed surface, dispersion of wiring decreases thereby decreasing dispersion of impedance.

摘要翻译： 本发明提供一种实现细小间距的多层印刷线路板。 在多层印刷线路板和层间树脂绝缘层中并入耐热基板，并将导电层交替放置在耐热基板上。 形成各导电层通过通孔连接的叠层布线板。 通过使用由Si衬底构成的耐热衬底，在镜面处理的Si衬底的表面上形成通孔，从而可以形成比其表面不均匀的树脂衬底更细的布线，从而实现细小的间距。 此外，通过在镜面处理表面上形成布线，布线的分散减小，从而减小阻抗的分散。

公开(公告)号：US20070187140A1

公开(公告)日：2007-08-16

申请号：US11566912

申请日：2006-12-05

申请人： Takashi Kariya ,  Toshiki Furutani ,  Takeshi Kawanishi

发明人： Takashi Kariya ,  Toshiki Furutani ,  Takeshi Kawanishi

IPC分类号： H05K1/16

CPC分类号： H05K3/326 ,  H01L23/49811 ,  H01L24/72 ,  H01L24/81 ,  H01L24/90 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/3011 ,  H05K3/28 ,  H05K3/341 ,  H05K3/4092 ,  H05K2201/0311 ,  H05K2201/0314 ,  H05K2201/0397 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599

摘要： The present invention is to provide a printed wiring board in which malconnection or disconnection caused by a difference between coefficients of thermal expansion of a semiconductor chip and a printed wiring board can be decreased even when a highly-integrated semiconductor apparatus is mounted thereon and an electronic device using the same. An electronic device (4) according to the present invention includes a printed wiring board (1) with a component mounting pin (18) and a surface-mounting type semiconductor apparatus (2) with an electrode pad (3), wherein the component mounting pin (18) has elasticity and is urged against the electrode pad (3) to maintain electric connection.

摘要翻译： 本发明是提供一种印刷电路板，其中即使在高度集成的半导体装置安装在其上时也能够降低由半导体芯片和印刷电路板的热膨胀系数之间的差异引起的故障连接或断开，并且电子 设备使用相同。 根据本发明的电子设备（4）包括具有元件安装销（18）的印刷电路板（1）和具有电极焊盘（3）的表面安装型半导体设备（2），其中元件安装 销（18）具有弹性并且被推靠在电极焊盘（3）上以保持电连接。

公开(公告)号：US20060231290A1

公开(公告)日：2006-10-19

申请号：US11443046

申请日：2006-05-31

申请人： Takashi Kariya ,  Toshiki Furutani

发明人： Takashi Kariya ,  Toshiki Furutani

IPC分类号： H05K1/03 ,  H05K1/11

CPC分类号： H05K1/0271 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/0373 ,  H05K1/115 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/068 ,  H05K2201/10674 ,  Y10T29/49126 ,  Y10T29/49151 ,  Y10T29/49162 ,  H01L2224/0401

摘要： A multilayer printed wiring board 10 includes: a build-up layer 30 that is formed on a core substrate 20 and has a conductor pattern 32 disposed on an upper surface; a low elastic modulus layer 40 that is formed on the build-up layer 30; lands 52 that are disposed on an upper surface of the low elastic modulus layer 40 and connected via solder bumps 66 to a IC chip 70; and conductor posts 50 that pass through the low elastic modulus layer 40 and electrically connect lands 52 with conductor patterns 32. The conductor posts 50 have the aspect ratio Rasp (height/minimum diameter) of not less than 4 and the minimum diameter exceeding 30 μm, and the aspect ratio Rasp of external conductor posts 50a, which are positioned at external portions of the low elastic modulus layer 40, is greater than or equal to the aspect ratio Rasp of internal conductor posts 50b, which are positioned at internal portions of the low elastic modulus layer 40.

摘要翻译： 多层印刷布线板10包括：形成在芯基板20上并具有布置在上表面上的导体图案32的堆积层30; 形成在积层30上的低弹性模量层40; 焊盘52设置在低弹性模量层40的上表面上并通过焊料凸块66连接到IC芯片70; 以及穿过低弹性模量层40并将焊盘52与导体图案32电连接的导体柱50.导体柱50的纵横比Rasp（高度/最小直径）不小于4，最小直径超过30μm ，并且位于低弹性模量层40的外部的外部导体柱50a的纵横比Rasp大于或等于位于内部部分的内部导体柱50b的纵横比Rasp 的低弹性模量层40。

公开(公告)号：US08975742B2

公开(公告)日：2015-03-10

申请号：US13598751

申请日：2012-08-30

申请人： Toshiki Furutani ,  Takeshi Furusawa

发明人： Toshiki Furutani ,  Takeshi Furusawa

IPC分类号： H01L23/12 ,  H01L23/053 ,  H01L23/495 ,  H01L23/498

CPC分类号： H01L23/49541 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/3511

摘要： A printed wiring board includes a substrate, a first buildup formed on a first surface of the substrate and including the outermost conductive layer, and a second buildup layer formed on a second surface of the substrate and including the outermost conductive layer. The outermost layer of the first buildup has pads positioned to connect a semiconductor component, the first buildup has a component mounting region directly under the component such that the outermost layer of the first buildup has a portion in the region, the outermost layer of the second buildup has a portion directly under the region, and the portions satisfy the ratio in the range of from 1.1 to 1.35, where the ratio is obtained by dividing a planar area of the portion of the second buildup by a planar area of the portion of the first buildup.

摘要翻译： 印刷布线板包括基板，形成在基板的第一表面上并且包括最外面的导电层的第一累积物和形成在基板的第二表面上并且包括最外面导电层的第二累积层。 第一堆积的最外层具有定位成连接半导体部件的焊盘，第一堆积具有直接在部件下方的部件安装区域，使得第一堆积物的最外层具有该区域中的一部分，第二部分的最外层 积聚部分具有直接在该区域下方的部分，并且这些部分满足在1.1至1.35范围内的比率，其中通过将第二聚集部分的平面面积除以该部分的平面面积获得的比例 第一次积累

公开(公告)号：US08957320B2

公开(公告)日：2015-02-17

申请号：US13558892

申请日：2012-07-26

申请人： Toshiki Furutani ,  Yukinobu Mikado ,  Shunsuke Sakai ,  Yusuke Tanaka

发明人： Toshiki Furutani ,  Yukinobu Mikado ,  Shunsuke Sakai ,  Yusuke Tanaka

IPC分类号： H05K1/16 ,  H05K1/18 ,  H05K1/02 ,  H05K3/46

CPC分类号： H05K1/162 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/185 ,  H05K3/4661

摘要： A printed wiring board includes a substrate having an accommodation section having multiple opening portions, multiple electronic components accommodated in the opening portions, respectively, a filler resin provided in the opening portions in the substrate such that the electronic components are secured in the opening portions in the substrate, a resin insulation layer formed over the substrate and the electronic components, a conductive layer formed on the resin insulation layer, and via conductors formed in the resin insulation layer and connecting the conductive layer and the electronic components. The opening portions are connected to each other.

摘要翻译： 印刷电路板包括具有多个开口部分的容纳部分的基板，分别容纳在开口部分中的多个电子部件，设置在基板的开口部分中的填充树脂，使得电子部件固定在开口部分中 基板，形成在基板上的树脂绝缘层和电子部件，形成在树脂绝缘层上的导电层和形成在树脂绝缘层中并连接导电层和电子部件的通孔导体。 开口部彼此连接。

公开(公告)号：US08923008B2

公开(公告)日：2014-12-30

申请号：US13404173

申请日：2012-02-24

申请人： Kazuhiro Yoshikawa ,  Toshiki Furutani

发明人： Kazuhiro Yoshikawa ,  Toshiki Furutani

IPC分类号： H05K1/18 ,  H05K7/12 ,  H01L21/56 ,  H01L25/10 ,  H01L23/31

CPC分类号： H05K1/188 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45147 ,  H01L2224/73204 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K1/185 ,  H05K2201/10674 ,  H05K2203/1469 ,  Y10T29/49139 ,  Y10T29/49146 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/01005 ,  H01L2924/01033

摘要： A circuit board includes an insulation layer having a first surface and a second surface on the opposite side of the first surface, an electronic component positioned in the insulation layer and having a terminal, a conductive pattern formed on the second surface of the insulation layer and electrically connected to the terminal, and an insulative film formed on the second surface of the insulation layer and on the conductive pattern. The terminal of the electronic component has a protruding portion which protrudes from the second surface of the insulation layer.

摘要翻译： 电路板包括具有第一表面和与第一表面相对的第二表面的绝缘层，位于绝缘层中并具有端子的电子部件，形成在绝缘层的第二表面上的导电图案， 电连接到端子，以及形成在绝缘层的第二表面上和导电图案上的绝缘膜。 电子部件的端子具有从绝缘层的第二表面突出的突出部分。