公开(公告)号：US09287386B2

公开(公告)日：2016-03-15

申请号：US14320559

申请日：2014-06-30

Applicant: Applied Materials, Inc.

Inventor： Ying Zhang ,  Hua Chung

IPC: H01L21/00 ,  H01L29/00 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/161 ,  H01L29/16 ,  H01L21/02

CPC classification number: H01L29/66795 ,  B82Y10/00 ,  B82Y40/00 ,  H01J37/32357 ,  H01J37/32449 ,  H01J37/32541 ,  H01J37/32568 ,  H01L21/02233 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/02359 ,  H01L21/02603 ,  H01L21/02606 ,  H01L21/265 ,  H01L21/30621 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/324 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66666 ,  H01L29/775

Abstract: Embodiments of the present disclosure provide methods for forming nanowire structures with desired materials for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips. In one embodiment, a method of forming nanowire structures on a substrate includes forming a multi-material layer on a substrate, wherein the multi-material layer includes repeating pairs of a first layer and a second layer, the substrate further comprising a patterned hardmask layer disposed on the multi-material layer, etching the multi-material layer through openings defined by the patterned hardmask layer to expose sidewalls of the first and the second layer of the multi-material layer, and laterally and selectively etching the second layer from the substrate.

Abstract translation: 本公开的实施例提供了用于形成用于半导体芯片的鳍式场效应晶体管（FinFET）的三维（3D）堆叠的所需材料的纳米线结构的方法。 在一个实施方案中，在衬底上形成纳米线结构的方法包括在衬底上形成多材料层，其中所述多材料层包括第一层和第二层的重复对，所述衬底还包括图案化硬掩模层 设置在多材料层上，通过由图案化的硬掩模层限定的开口蚀刻多材料层，以暴露多材料层的第一和第二层的侧壁，并横向和选择性地从衬底上蚀刻第二层 。

公开(公告)号：US20150228503A1

公开(公告)日：2015-08-13

申请号：US14175379

申请日：2014-02-07

Applicant: Applied Materials, Inc.

Inventor： Ying Zhang ,  Hua Chung

IPC: H01L21/3213 ,  H01L21/033

CPC classification number: H01L21/3065 ,  H01J37/321 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/76224 ,  H01L29/66795 ,  H01L29/7848

Abstract: Embodiments may involve a method of semiconductor patterning, which includes patterning a first hardmask layer on top of a second hardmask layer. This patterning may define a feature with a first width. The method may encompass reducing the first width to a second width, where the second width is less than or equal to 10 nm. The method may include patterning the second hardmask layer to define a patterned second hardmask layer. The method may involve etching a semiconductor substrate underlying the second hardmask layer to define a fin structure with a third width of less than or equal to 10 nm.

Abstract translation: 实施例可以包括半导体图案化的方法，其包括在第二硬掩模层的顶部上构图第一硬掩模层。 该图案化可以限定具有第一宽度的特征。 该方法可以包括将第一宽度减小到第二宽度，其中第二宽度小于或等于10nm。 该方法可以包括图案化第二硬掩模层以限定图案化的第二硬掩模层。 该方法可以包括蚀刻第二硬掩模层下面的半导体衬底以限定具有小于或等于10nm的第三宽度的鳍结构。

公开(公告)号：US11643721B2

公开(公告)日：2023-05-09

申请号：US16129232

申请日：2018-09-12

Applicant: Applied Materials, Inc.

Inventor： Feng Q. Liu ,  Hua Chung ,  Schubert Chu ,  Mei Chang ,  Jeffrey W. Anthis ,  David Thompson

IPC: C23C16/42 ,  C23C16/513 ,  C23C16/455 ,  C23C16/52 ,  C23C16/507 ,  C23C16/14

CPC classification number: C23C16/42 ,  C23C16/14 ,  C23C16/45536 ,  C23C16/45542 ,  C23C16/507 ,  C23C16/513 ,  C23C16/52

Abstract: Processing methods for forming iridium-containing films at low temperatures are described. The methods comprise exposing a substrate to iridium hexafluoride and a reactant to form iridium metal or iridium silicide films. Methods for enhancing selectivity and tuning the silicon content of some films are also described.

公开(公告)号：US09978596B2

公开(公告)日：2018-05-22

申请号：US15377629

申请日：2016-12-13

Applicant: Applied Materials, Inc.

Inventor： Ying Zhang ,  Uday Mitra ,  Praburam Gopalraja ,  Srinivas D. Nemani ,  Hua Chung

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/0332 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76816

Abstract: The present disclosure provides forming nanostructures with precision dimension control and minimum lithographic related errors for features with dimension under 14 nanometers and beyond. A self-aligned multiple spacer patterning (SAMSP) process is provided herein and the process utilizes minimum lithographic exposure process, but rather multiple deposition/etching process to incrementally reduce feature sizes formed in the mask along the manufacturing process, until a desired extreme small dimension nanostructures are formed in a mask layer.

公开(公告)号：US09373546B2

公开(公告)日：2016-06-21

申请号：US14864389

申请日：2015-09-24

Applicant: Applied Materials, Inc.

Inventor： Ying Zhang ,  Hua Chung

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L27/12 ,  H01L21/311

CPC classification number: H01L21/823431 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02587 ,  H01L21/02658 ,  H01L21/02664 ,  H01L21/31116 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods and apparatus for forming FinFET structures are provided. Selective etching and deposition processes described herein may provide for FinFET manufacturing without the utilization of multiple patterning processes. Embodiments described herein also provide for fin material manufacturing methods for transitioning from silicon to III-V materials while maintaining acceptable crystal lattice orientations of the various materials utilized. Further embodiments provide etching apparatus which may be utilized to perform the methods described herein.

Abstract translation: 提供了用于形成FinFET结构的方法和装置。 本文所述的选择性蚀刻和沉积工艺可以提供FinFET制造而不利用多个图案化工艺。 本文描述的实施例还提供了用于从硅转变为III-V材料的翅片材料制造方法，同时保持所使用的各种材料的可接受的晶格取向。 另外的实施例提供可用于执行本文所述方法的蚀刻装置。

公开(公告)号：US09209279B1

公开(公告)日：2015-12-08

申请号：US14484645

申请日：2014-09-12

Applicant: Applied Materials, Inc.

Inventor： Ying Zhang ,  Hua Chung

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/823431 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02587 ,  H01L21/02658 ,  H01L21/02664 ,  H01L21/31116 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods and apparatus for forming FinFET structures are provided. Selective etching and deposition processes described herein may provide for FinFET manufacturing without the utilization of multiple patterning processes. Embodiments described herein also provide for fin material manufacturing methods for transitioning from silicon to III-V materials while maintaining acceptable crystal lattice orientations of the various materials utilized. Further embodiments provide etching apparatus which may be utilized to perform the methods described herein.

Abstract translation: 提供了用于形成FinFET结构的方法和装置。 本文所述的选择性蚀刻和沉积工艺可以提供FinFET制造而不利用多个图案化工艺。 本文描述的实施例还提供了用于从硅转变为III-V材料的翅片材料制造方法，同时保持所使用的各种材料的可接受的晶格取向。 另外的实施例提供可用于执行本文所述方法的蚀刻装置。

公开(公告)号：US09031685B2

公开(公告)日：2015-05-12

申请号：US14149560

申请日：2014-01-07

Applicant: Applied Materials, Inc.

Inventor： Barry L. Chin ,  Alfred W. Mak ,  Lawrence C. Lei ,  Ming Xi ,  Hua Chung ,  Ken Kaung Lai ,  Jeong Soo Byun

IPC: G06F19/00 ,  C23C16/455 ,  C23C16/458

CPC classification number: C23C16/45544 ,  C23C16/45525 ,  C23C16/45548 ,  C23C16/45551 ,  C23C16/4583

Abstract: A method and apparatus for atomic layer deposition (ALD) is described. In one embodiment, an apparatus comprises a vacuum chamber body having a contiguous internal volume comprised of a first deposition region spaced-apart from a second deposition region, the chamber body having a feature operable to minimize intermixing of gases between the first and the second deposition regions, a first gas port formed in the chamber body and positioned to pulse gas preferentially to the first deposition region to enable a first deposition process to be performed in the first deposition region, and a second gas port formed in the chamber body and positioned to pulse gas preferentially to the second deposition region to enable a second deposition process to be performed in the second deposition region is provided.

Abstract translation: 描述了用于原子层沉积（ALD）的方法和装置。 在一个实施例中，一种装置包括具有连续的内部容积的真空室主体，其包括与第二沉积区域间隔开的第一沉积区域，所述室主体具有可操作以最小化第一和第二沉积物之间的气体混合的特征 区域，形成在所述室主体中并且定位成优先地将气体脉冲至所述第一沉积区域的第一气体端口，以使得能够在所述第一沉积区域中执行第一沉积工艺，以及形成在所述室主体中并定位成 优选提供脉冲气体到第二沉积区域以使得能够在第二沉积区域中进行第二沉积工艺。

公开(公告)号：US20240200188A1

公开(公告)日：2024-06-20

申请号：US18590141

申请日：2024-02-28

Applicant: Applied Materials, Inc.

Inventor： Feng Q. Liu ,  Hua Chung ,  Schubert Chu ,  Mei Chang ,  Jeffrey W. Anthis ,  David Thompson

IPC: C23C16/42 ,  C23C16/14 ,  C23C16/455 ,  C23C16/507 ,  C23C16/513 ,  C23C16/52

CPC classification number: C23C16/42 ,  C23C16/14 ,  C23C16/45536 ,  C23C16/45542 ,  C23C16/507 ,  C23C16/513 ,  C23C16/52

Abstract: Processing methods for forming iridium-containing films at low temperatures are described. The methods comprise exposing a substrate to iridium hexafluoride and a reactant to form iridium metal or iridium silicide films. Methods for enhancing selectivity and tuning the silicon content of some films are also described.

公开(公告)号：US11124874B2

公开(公告)日：2021-09-21

申请号：US16561780

申请日：2019-09-05

Applicant: Applied Materials, Inc.

Inventor： Hua Chung ,  Feng Q. Liu ,  Schubert Chu

IPC: C23C16/06 ,  C23C16/455

Abstract: Methods for depositing one or more iridium materials on a surface of a substrate are provided. A method for forming the iridium material (e.g., metallic iridium and/or iridium silicide) on the substrate can include sequentially exposing the substrate to an iridium precursor and a reducing agent during an atomic layer deposition (ALD) process within a process chamber and depositing the iridium material on the substrate. In some examples, the reducing agent can be or include hydrogen gas (H2), a hydrogen plasma, atomic hydrogen, hydrazine or derivatives thereof, or any combination thereof and the deposited iridium material is metallic iridium. In other examples, the reducing agent contains one or more silicon precursors and the iridium material is an iridium silicide.

公开(公告)号：US11011635B2

公开(公告)日：2021-05-18

申请号：US15839024

申请日：2017-12-12

Applicant: Applied Materials, Inc.

Inventor： Sheng-Chin Kung ,  Hua Chung

IPC: H01L29/00 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/10 ,  H01L29/161

Abstract: The present disclosure generally relates to devices having conformal semiconductor cladding materials, and methods of forming the same. The cladding material is a silicon germanium epitaxial material. The cladding material is capable of being deposited to a thickness which is less than cladding materials formed by conventional deposition/etch techniques.