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31.发明申请Semiconductor Device and Method of Forming Leadframe Interposer Over Semiconductor Die and TSV Substrate for Vertical Electrical Interconnect 有权半导体器件和形成用于垂直电互连的半导体芯片和TSV基板的引线框架插入件的方法公开(公告)号：US20120061814A1
公开(公告)日：2012-03-15
申请号：US12882110
申请日：2010-09-14
IPC分类号： H01L23/495 , H01L21/60
CPC分类号： H01L23/495 , H01L21/4832 , H01L21/4853 , H01L21/56 , H01L21/563 , H01L23/3107 , H01L23/3128 , H01L23/3135 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L24/03 , H01L24/05 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/0401 , H01L2224/04042 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/06131 , H01L2224/16225 , H01L2224/29144 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48105 , H01L2224/48157 , H01L2224/48175 , H01L2224/48227 , H01L2224/48228 , H01L2224/48247 , H01L2224/49113 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/81411 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/831 , H01L2225/06517 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/01079 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/157 , H01L2924/1579 , H01L2924/181 , H01L2924/1815 , H01L2924/3511 , H05K2203/0384 , H01L2924/01014 , H01L2924/0665 , H01L2924/00 , H01L2924/00012 , H01L2224/81805 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device has a substrate with a plurality of conductive vias formed through the substrate and first conductive layer formed over the substrate. A first semiconductor die is mounted over the substrate. A second semiconductor die can be mounted over the first semiconductor die. A leadframe interposer has a base plate and a plurality of base leads extending from the base plate. An etch-resistant conductive layer is formed over a surface of the base plate opposite the base leads. The leadframe is mounted to the substrate over the first semiconductor die. An encapsulant is deposited over the substrate and first semiconductor die. The base plate is removed while retaining the etch-resistant conductive layer and portion of the base plate opposite the base leads to electrically isolate the base leads. An interconnect structure is formed over a surface of the substrate opposite the base leads.
摘要翻译： 半导体器件具有衬底，其具有通过衬底形成的多个导电通孔和形成在衬底上的第一导电层。 第一半导体管芯安装在衬底上。 第二半导体管芯可以安装在第一半导体管芯上。 引线框架插入件具有基板和从基板延伸的多个基底引线。 在与基极相对的基板的表面上形成耐蚀刻导电层。 引线框架安装在第一半导体管芯上的衬底上。 密封剂沉积在衬底和第一半导体管芯上。 去除基板，同时保持耐蚀刻导电层，并且基板的与基底引线相对的部分电绝缘基极。 在与基极相对的基板的表面上形成互连结构。
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32.发明申请Semiconductor Device and Method of Forming Wafer Level Multi-Row Etched Lead Package 有权半导体器件和形成晶圆级多行蚀刻引线封装的方法公开(公告)号：US20110215449A1
公开(公告)日：2011-09-08
申请号：US12719476
申请日：2010-03-08
CPC分类号： H01L21/56 , H01L23/28 , H01L25/11 , H01L2224/04105 , H01L2224/12105 , H01L2224/24247 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48229 , H01L2224/48235 , H01L2224/73265 , H01L2224/73267 , H01L2224/92244 , H01L2924/01322 , H01L2924/13091 , H01L2924/15153 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device has a base carrier having first and second opposing surfaces. The first surface of the base carrier is etched to form a plurality of cavities and multiple rows of base leads between the cavities extending between the first and second surfaces. A second conductive layer is formed over the second surface of the base carrier. A semiconductor die is mounted within a cavity of the base carrier. A first insulating layer is formed over the die and first surface of the base carrier and into the cavities. A first conductive layer is formed over the first insulating layer and first surface of the base carrier. A second insulating layer is formed over the first insulating layer and first conductive layer. A portion of the second surface of the base carrier is removed to expose the first insulating layer and electrically isolate the base leads.
摘要翻译： 半导体器件具有具有第一和第二相对表面的基底载体。 基底托架的第一表面被蚀刻以形成在第一和第二表面之间延伸的空腔之间的多个空腔和多排基底引线。 第二导电层形成在基底载体的第二表面上。 半导体管芯安装在基座的空腔内。 第一绝缘层形成在基体载体的模具和第一表面上并进入空腔中。 在第一绝缘层和基底载体的第一表面上形成第一导电层。 在第一绝缘层和第一导电层上形成第二绝缘层。 去除基底载体的第二表面的一部分以露出第一绝缘层并电绝缘基极。
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33.发明授权Semiconductor device and method of forming wafer level multi-row etched lead package 有权半导体器件和晶圆级多行蚀刻引线封装形成方法公开(公告)号：US08241956B2
公开(公告)日：2012-08-14
申请号：US12719476
申请日：2010-03-08
IPC分类号： H01L21/00
CPC分类号： H01L21/56 , H01L23/28 , H01L25/11 , H01L2224/04105 , H01L2224/12105 , H01L2224/24247 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48229 , H01L2224/48235 , H01L2224/73265 , H01L2224/73267 , H01L2224/92244 , H01L2924/01322 , H01L2924/13091 , H01L2924/15153 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device has a base carrier having first and second opposing surfaces. The first surface of the base carrier is etched to form a plurality of cavities and multiple rows of base leads between the cavities extending between the first and second surfaces. A second conductive layer is formed over the second surface of the base carrier. A semiconductor die is mounted within a cavity of the base carrier. A first insulating layer is formed over the die and first surface of the base carrier and into the cavities. A first conductive layer is formed over the first insulating layer and first surface of the base carrier. A second insulating layer is formed over the first insulating layer and first conductive layer. A portion of the second surface of the base carrier is removed to expose the first insulating layer and electrically isolate the base leads.
摘要翻译： 半导体器件具有具有第一和第二相对表面的基底载体。 基底托架的第一表面被蚀刻以形成在第一和第二表面之间延伸的空腔之间的多个空腔和多排基底引线。 第二导电层形成在基底载体的第二表面上。 半导体管芯安装在基座的空腔内。 第一绝缘层形成在基体载体的模具和第一表面上并进入空腔中。 在第一绝缘层和基底载体的第一表面上形成第一导电层。 在第一绝缘层和第一导电层上形成第二绝缘层。 去除基底载体的第二表面的一部分以露出第一绝缘层并电绝缘基极。
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34.发明申请Semiconductor Device and Method of Forming Wafer-Level Multi-Row Etched Leadframe With Base Leads and Embedded Semiconductor Die 有权半导体器件及其基片和嵌入式半导体晶片级晶圆多列蚀刻引线框的形成方法公开(公告)号：US20120038064A1
公开(公告)日：2012-02-16
申请号：US13284811
申请日：2011-10-28
CPC分类号： H01L24/29 , H01L21/4832 , H01L23/49548 , H01L23/49575 , H01L23/49582 , H01L24/16 , H01L24/19 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/85 , H01L24/92 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/29111 , H01L2224/2919 , H01L2224/32014 , H01L2224/32145 , H01L2224/48247 , H01L2224/73253 , H01L2224/73265 , H01L2224/73267 , H01L2224/81191 , H01L2224/81411 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/83805 , H01L2224/85411 , H01L2224/85424 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2224/85455 , H01L2224/92247 , H01L2225/0651 , H01L2225/06517 , H01L2225/06558 , H01L2225/1023 , H01L2225/1029 , H01L2225/1035 , H01L2225/1052 , H01L2225/1058 , H01L2225/107 , H01L2924/00011 , H01L2924/00014 , H01L2924/01014 , H01L2924/01029 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/12041 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1432 , H01L2924/1433 , H01L2924/14335 , H01L2924/1434 , H01L2924/15311 , H01L2924/1579 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2924/0105 , H01L2924/01082 , H01L2924/00012 , H01L2224/13111 , H01L2924/0665 , H01L2224/81805
摘要： A semiconductor device has a base substrate with first and second opposing surfaces. A plurality of cavities and base leads between the cavities is formed in the first surface of the base substrate. The first set of base leads can have a different height or similar height as the second set of base leads. A concave capture pad can be formed over the second set of base leads. Alternatively, a plurality of openings can be formed in the base substrate and the semiconductor die mounted to the openings. A semiconductor die is mounted between a first set of the base leads and over a second set of the base leads. An encapsulant is deposited over the die and base substrate. A portion of the second surface of the base substrate is removed to separate the base leads. An interconnect structure is formed over the encapsulant and base leads.
摘要翻译： 半导体器件具有带有第一和第二相对表面的基底基板。 在基底基板的第一表面中形成有在空腔之间的多个空腔和基底引线。 第一组基线可以具有与第二组基线不同的高度或相似的高度。 可以在第二组基线上形成凹形捕获垫。 或者，可以在基底基板和安装到开口的半导体管芯上形成多个开口。 半导体管芯安装在第一组基极引线之间和第二组基极引线之间。 密封剂沉积在管芯和基底衬底上。 去除基底基板的第二表面的一部分以分离基底引线。 在密封剂和基底引线上形成互连结构。
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35.发明授权Semiconductor device and method of forming leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect 有权在半导体管芯上形成引线框架插入件的半导体器件和方法以及用于垂直电互连的TSV衬底公开(公告)号：US08409922B2
公开(公告)日：2013-04-02
申请号：US12882110
申请日：2010-09-14
IPC分类号： H01L21/00 , H01L23/495
CPC分类号： H01L23/495 , H01L21/4832 , H01L21/4853 , H01L21/56 , H01L21/563 , H01L23/3107 , H01L23/3128 , H01L23/3135 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L24/03 , H01L24/05 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/0401 , H01L2224/04042 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/06131 , H01L2224/16225 , H01L2224/29144 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48105 , H01L2224/48157 , H01L2224/48175 , H01L2224/48227 , H01L2224/48228 , H01L2224/48247 , H01L2224/49113 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/81411 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/831 , H01L2225/06517 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/01079 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/157 , H01L2924/1579 , H01L2924/181 , H01L2924/1815 , H01L2924/3511 , H05K2203/0384 , H01L2924/01014 , H01L2924/0665 , H01L2924/00 , H01L2924/00012 , H01L2224/81805 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device has a substrate with a plurality of conductive vias formed through the substrate and first conductive layer formed over the substrate. A first semiconductor die is mounted over the substrate. A second semiconductor die can be mounted over the first semiconductor die. A leadframe interposer has a base plate and a plurality of base leads extending from the base plate. An etch-resistant conductive layer is formed over a surface of the base plate opposite the base leads. The leadframe is mounted to the substrate over the first semiconductor die. An encapsulant is deposited over the substrate and first semiconductor die. The base plate is removed while retaining the etch-resistant conductive layer and portion of the base plate opposite the base leads to electrically isolate the base leads. An interconnect structure is formed over a surface of the substrate opposite the base leads.
摘要翻译： 半导体器件具有衬底，其具有通过衬底形成的多个导电通孔和形成在衬底上的第一导电层。 第一半导体管芯安装在衬底上。 第二半导体管芯可以安装在第一半导体管芯上。 引线框架插入件具有基板和从基板延伸的多个基底引线。 在与基极相对的基板的表面上形成耐蚀刻导电层。 引线框架安装在第一半导体管芯上的衬底上。 密封剂沉积在衬底和第一半导体管芯上。 去除基板，同时保持耐蚀刻导电层，并且基板的与基底引线相对的部分电绝缘基极。 在与基极相对的基板的表面上形成互连结构。
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36.发明授权Semiconductor device and method of forming wafer-level multi-row etched leadframe with base leads and embedded semiconductor die 有权用基极引线和嵌入式半导体芯片形成晶圆级多行蚀刻引线框的半导体器件和方法公开(公告)号：US08076184B1
公开(公告)日：2011-12-13
申请号：US12857395
申请日：2010-08-16
CPC分类号： H01L24/29 , H01L21/4832 , H01L23/49548 , H01L23/49575 , H01L23/49582 , H01L24/16 , H01L24/19 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/85 , H01L24/92 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/29111 , H01L2224/2919 , H01L2224/32014 , H01L2224/32145 , H01L2224/48247 , H01L2224/73253 , H01L2224/73265 , H01L2224/73267 , H01L2224/81191 , H01L2224/81411 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/83805 , H01L2224/85411 , H01L2224/85424 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2224/85455 , H01L2224/92247 , H01L2225/0651 , H01L2225/06517 , H01L2225/06558 , H01L2225/1023 , H01L2225/1029 , H01L2225/1035 , H01L2225/1052 , H01L2225/1058 , H01L2225/107 , H01L2924/00011 , H01L2924/00014 , H01L2924/01014 , H01L2924/01029 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/12041 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1432 , H01L2924/1433 , H01L2924/14335 , H01L2924/1434 , H01L2924/15311 , H01L2924/1579 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2924/0105 , H01L2924/01082 , H01L2924/00012 , H01L2224/13111 , H01L2924/0665 , H01L2224/81805
摘要： A semiconductor device has a base carrier with first and second opposing surfaces. A plurality of cavities and base leads between the cavities is formed in the first surface of the base carrier. The first set of base leads can have a different height or similar height as the second set of base leads. A concave capture pad can be formed over the second set of base leads. Alternatively, a plurality of openings can be formed in the base carrier and the semiconductor die mounted to the openings. A semiconductor die is mounted between a first set of the base leads and over a second set of the base leads. An encapsulant is deposited over the die and base carrier. A portion of the second surface of the base carrier is removed to separate the base leads. An interconnect structure is formed over the encapsulant and base leads.
摘要翻译： 半导体器件具有带有第一和第二相对表面的基底载体。 在基座的第一表面中形成有空腔之间的多个空腔和底座引线。 第一组基线可以具有与第二组基线不同的高度或相似的高度。 可以在第二组基线上形成凹形捕获垫。 或者，可以在基座载体和安装到开口的半导体管芯上形成多个开口。 半导体管芯安装在第一组基极引线之间和第二组基极引线之间。 密封剂沉积在管芯和基底载体上。 移除基底载体的第二表面的一部分以分离基底引线。 在密封剂和基底引线上形成互连结构。
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37.发明授权Stackable integrated circuit package system with multiple interconnect interface 有权具有多个互连接口的可堆叠集成电路封装系统公开(公告)号：US08232658B2
公开(公告)日：2012-07-31
申请号：US12113888
申请日：2008-05-01
IPC分类号： H01L23/31
CPC分类号： H01L21/561 , H01L21/568 , H01L23/3107 , H01L23/3128 , H01L23/3135 , H01L23/49551 , H01L24/14 , H01L24/17 , H01L24/48 , H01L24/73 , H01L25/03 , H01L25/105 , H01L2224/13099 , H01L2224/1403 , H01L2224/141 , H01L2224/16245 , H01L2224/274 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/73204 , H01L2224/73265 , H01L2225/06558 , H01L2225/1029 , H01L2225/1058 , H01L2924/00014 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A stackable integrated circuit package system includes: forming a first integrated circuit die having a small interconnect and a large interconnect provided thereon; forming an external interconnect, having an upper tip and a lower tip, from a lead frame; mounting the first integrated circuit die on the external interconnect with the small interconnect on the lower tip and below the upper tip; and encapsulating around the small interconnect and around the large interconnect with an exposed surface.
摘要翻译： 一种可堆叠的集成电路封装系统，包括：形成具有小互连的第一集成电路管芯和设置在其上的大的互连; 从引线框架形成具有上端和下端的外部互连件; 将第一集成电路管芯安装在外部互连上，并在下部尖端上方和上部尖端上方具有小互连; 并且围绕小互连并围绕具有暴露表面的大互连围绕。
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38.发明申请INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTIPLE ROW LEADS AND METHOD OF MANUFACTURE THEREOF 有权具有多条引线的集成电路包装系统及其制造方法公开(公告)号：US20120146203A1
公开(公告)日：2012-06-14
申请号：US12968266
申请日：2010-12-14
IPC分类号： H01L23/495 , H01L21/50
CPC分类号： H01L21/4832 , H01L23/3107 , H01L23/49548 , H01L23/49582 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05554 , H01L2224/32245 , H01L2224/48247 , H01L2224/48257 , H01L2224/49171 , H01L2224/73265 , H01L2224/92247 , H01L2924/00013 , H01L2924/00014 , H01L2924/10162 , H01L2924/14 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method of manufacture of an integrated circuit packaging system includes: forming a base structure having a die paddle, an outer lead, and an inner lead between the die paddle and the outer lead, with a pre-plated finish on a base structure system side of the base structure; mounting an integrated circuit device to a side of the die paddle opposite the paddle system side; attaching an interconnect to the integrated circuit device and a side of the inner lead opposite the inner lead system side; applying an encapsulation around the integrated circuit device, the interconnect, and the base structure with the pre-plated finish exposed from the encapsulation; and forming an inward channel in the encapsulation to electrically isolate the inner lead.
摘要翻译： 一种集成电路封装系统的制造方法，其特征在于，在基板结构系统侧，形成具有模板，外引线和芯片和外引线之间的内引线的基体结构 的基础结构; 将集成电路装置安装在与所述桨叶系统侧相对的所述模桨的一侧; 将互连件连接到集成电路器件和内引线的与内引线系统侧相对的一侧; 在集成电路器件，互连和基底结构周围施加封装，其中从封装暴露出的预镀完成; 以及在所述封装中形成向内的沟道，以使所述内部引线电隔离。
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公开(公告)号：US07986043B2
公开(公告)日：2011-07-26
申请号：US11276646
申请日：2006-03-08
IPC分类号： H01L23/48
CPC分类号： H01L23/3128 , H01L23/3135 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L25/105 , H01L2224/16145 , H01L2224/32225 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/73207 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06568 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01067 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19104 , H01L2924/00015 , H01L2224/05599 , H01L2924/00 , H01L2924/00012
摘要： An integrated circuit package on package system including forming an interconnect integrated circuit package and attaching an extended-lead integrated circuit package on the interconnect integrated circuit package wherein a mold cap of the extended-lead integrated circuit package faces a mold cap of the interconnect integrated circuit package.
摘要翻译： 一种集成电路封装在封装系统上，包括形成互连集成电路封装并将互连集成电路封装上的扩展引线集成电路封装，其中延伸引线集成电路封装的模帽面向互连集成电路的模具盖 包。
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公开(公告)号：US07868434B2
公开(公告)日：2011-01-11
申请号：US12730171
申请日：2010-03-23
IPC分类号： H01L23/495
CPC分类号： H01L25/105 , H01L23/3128 , H01L23/49833 , H01L23/49861 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/16225 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73204 , H01L2224/73265 , H01L2225/1005 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/01079 , H01L2924/078 , H01L2924/12041 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2924/00015 , H01L2224/05599 , H01L2224/0401
摘要： An integrated circuit package-on-package stacking system includes a leadframe interposer including: a leadframe having a lead; a molded base on a portion of the lead for only supporting the lead; and the leadframe interposer singulated from the leadframe, wherein the lead is bent to support a stack-up height.
摘要翻译： 一种集成电路封装堆叠堆叠系统，包括引线框架插入器，其包括：具有引线的引线框架; 在引线的一部分上仅用于支撑引线的模制基座; 并且引线框架插入器从引线框架分离，其中引线被弯曲以支撑堆叠高度。
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