公开(公告)号：US10204994B2

公开(公告)日：2019-02-12

申请号：US15477565

申请日：2017-04-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Andre P. Labonte ,  Lars W. Liebmann ,  Nigel G. Cave ,  Mark V. Raymond ,  Guillaume Bouche ,  David E. Brown

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L21/768 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3213

Abstract: One illustrative device disclosed herein includes, among other things, a stepped conductive source/drain structure with a first recess defined therein and a stepped final gate structure with a second recess defined therein, wherein, when viewed from above, the second recess is axially and laterally offset from the first recess. In this example, the device also includes a layer of insulating material positioned above the stepped conductive source/drain structure and the stepped final gate structure, a conductive gate (CB) contact that is conductively coupled to the stepped final gate structure and a conductive source/drain (CA) contact that is conductively coupled to the stepped conductive source/drain structure.

公开(公告)号：US10056458B2

公开(公告)日：2018-08-21

申请号：US14993537

申请日：2016-01-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chang Ho Maeng ,  Andy Wei ,  Anthony Ozzello ,  Bharat Krishnan ,  Guillaume Bouche ,  Haifeng Sheng ,  Haigou Huang ,  Huang Liu ,  Huy M. Cao ,  Ja-Hyung Han ,  SangWoo Lim ,  Kenneth A. Bates ,  Shyam Pal ,  Xintuo Dai ,  Jinping Liu

IPC: H01L21/3205 ,  H01L29/40 ,  H01L29/423 ,  H01L21/02 ,  H01L21/28 ,  H01L29/417

CPC classification number: H01L29/401 ,  H01L21/02126 ,  H01L21/02282 ,  H01L21/28229 ,  H01L21/76828 ,  H01L21/76837 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/78

Abstract: Methods of MOL S/D contact patterning of RMG devices without gouging of the Rx area or replacement of the dielectric are provided. Embodiments include forming a SOG layer around a RMG structure, the RMG structure having a contact etch stop layer and a gate cap layer; forming a lithography stack over the SOG and gate cap layers; patterning first and second TS openings through the lithography stack down to the SOG layer; removing a portion of the SOG layer through the first and second TS openings, the removing selective to the contact etch stop layer; converting the SOG layer to a SiO2 layer; forming a metal layer over the SiO2 layer; and planarizing the metal and SiO2 layers down to the gate cap layer.

公开(公告)号：US20180233585A1

公开(公告)日：2018-08-16

申请号：US15945578

申请日：2018-04-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L29/40 ,  H01L29/08

CPC classification number: H01L29/66795 ,  H01L21/76804 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/66 ,  H01L29/785

Abstract: Provided are approaches for forming merged gate and source/drain (S/D) contacts in a semiconductor device. Specifically, one approach provides a dielectric layer over a set of gate structures formed over a substrate; a set of source/drain (S/D) openings patterned in the dielectric layer between the gate structures; a fill material formed over the gate structures, including within the S/D openings; and a set of gate openings patterned over the gate structures, wherein a portion of the dielectric layer directly adjacent the fill material formed within one of the S/D openings is removed. The fill material is then removed, selective to the dielectric layer, and a metal material is deposited over the semiconductor device to form a set of gate contacts within the gate openings, and a set of S/D contacts within the S/D openings, wherein one of the gate contacts and one of the S/D contacts are merged.

公开(公告)号：US10026824B1

公开(公告)日：2018-07-17

申请号：US15408540

申请日：2017-01-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel Chanemougame ,  Andre Labonte ,  Ruilong Xie ,  Lars Liebmann ,  Nigel Cave ,  Guillaume Bouche

IPC: H01L29/49 ,  H01L23/535 ,  H01L29/66 ,  H01L21/768 ,  H01L29/06 ,  H01L21/306 ,  H01L21/84 ,  H01L21/28 ,  H01L27/12 ,  H01L27/092 ,  H01L27/088 ,  H01L29/78 ,  H01L29/417 ,  H01L21/02 ,  H01L29/40 ,  H01L21/764 ,  H01L21/8238 ,  H01L27/108 ,  H01L21/8234

Abstract: Disclosed are integrated circuit (IC) structures and formation methods. In the methods, a gate with a sacrificial gate cap and a sacrificial gate sidewall spacer is formed on a channel region. The cap and sidewall spacer are removed, creating a cavity with a lower portion between the sidewalls of the gate and adjacent metal plugs and with an upper portion above the lower portion and the gate. A first dielectric layer is deposited, forming an air-gap in the lower portion and lining the upper portion. A second dielectric layer is deposited, filling the upper portion. During formation of a gate contact opening (optionally over an active region), the second dielectric layer is removed and the first dielectric layer is anisotropically etched, thereby exposing the gate and creating a dielectric spacer with a lower air-gap segment and an upper solid segment. Metal deposited into the opening forms the gate contact.

公开(公告)号：US09899268B2

公开(公告)日：2018-02-20

申请号：US14644269

申请日：2015-03-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy C. Wei ,  Guillaume Bouche

IPC: H01L21/8238 ,  H01L29/10 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L21/823807 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/7851

Abstract: A method includes forming at least one fin in a semiconductor substrate. A fin spacer is formed on at least a first portion of the at least one fin. The fin spacer has an upper surface. The at least one fin is recessed to thereby define a recessed fin with a recessed upper surface that it is at a level below the upper surface of the fin spacer. A first epitaxial material is formed on the recessed fin. A lateral extension of the first epitaxial material is constrained by the fin spacer. A cap layer is formed on the first epitaxial material. The fin spacer is removed. The cap layer protects the first epitaxial material during the removal of the fin spacer.

公开(公告)号：US09812351B1

公开(公告)日：2017-11-07

申请号：US15379645

申请日：2016-12-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicholas Vincent Licausi ,  Guillaume Bouche ,  Lars Wolfgang Liebmann

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76816 ,  H01L23/528 ,  H01L23/5286

Abstract: A method includes patterning a 1st mandrel cell into a 1st mandrel layer disposed above a dielectric layer of a semiconductor structure. The 1st mandrel cell has 1st mandrels, 1st mandrel spaces and a mandrel cell pitch. A 2nd mandrel cell is patterned into a 2nd mandrel layer disposed above the 1st mandrel layer. The 2nd mandrel cell has 2nd mandrels, 2nd mandrel spaces, and the mandrel cell pitch. The 1st and 2nd mandrel cells are utilized to form metal line cells into the dielectric layer. The metal line cells have metal lines, spaces between the metal lines and a line cell pitch. The line cell pitch is equal to the mandrel cell pitch when the metal lines of the metal line cells are an even number. The line cell pitch is equal to half the mandrel cell pitch when the metal lines of the metal line cells are an odd number.

公开(公告)号：US09805988B1

公开(公告)日：2017-10-31

申请号：US15366514

申请日：2016-12-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven Bentley ,  Guillaume Bouche

IPC: H01L21/8238 ,  H01L21/84 ,  H01L29/78 ,  H01L29/36 ,  H01L29/66 ,  H01L21/266 ,  H01L21/324 ,  H01L27/12 ,  H01L27/092 ,  H01L27/088

CPC classification number: H01L21/845 ,  H01L21/266 ,  H01L21/324 ,  H01L21/823807 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/36 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785

Abstract: One aspect of the disclosure is directed to a method of forming a semiconductor structure including: forming a fin over a substrate within a device region, the fin including alternating layers of a sacrificial material and a semiconductor material, and including a lower channel region; forming a dopant-containing layer over the fin and the substrate; exposing an upper portion of the fin by removing the dopant-containing layer from the upper portion of the fin; removing the sacrificial material from the fin thereby suspending the semiconductor material within the fin between a pair of spacers and over the lower channel region of the fin; performing an anneal to drive in dopants from the dopant-containing layer to the lower channel region of the fin; and forming an active gate over the lower channel region of the fin and substantially surrounding the suspended semiconductor material over the lower channel region of the fin.

公开(公告)号：US09786545B1

公开(公告)日：2017-10-10

申请号：US15271519

申请日：2016-09-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Jason Eugene Stephens ,  Byoung Youp Kim ,  Craig Michael Child, Jr. ,  Shreesh Narasimha

IPC: H01L21/762 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/768

CPC classification number: H01L21/76224 ,  H01L21/0337 ,  H01L21/31051 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/528 ,  H01L27/0251

Abstract: A method includes providing a structure having a first hardmask layer, interposer layer, second hardmask layer and mandrel layer disposed respectively over a dielectric stack. An array of mandrels is patterned into the mandrel layer with a mandrel mask. An ANA trench is patterned into the mandrel layer with a first cut mask. The ANA trench is patterned into the interposer layer with a second cut mask. An organic planarization layer (OPL) is disposed over the structure. The OPL is etched to dispose it only in the ANA trench such that a top surface of the OPL is lower than the second hardmask layer. The structure is etched to form a pattern in a dielectric layer of the dielectric stack to form an array of metal lines in the dielectric layer, a portion of the pattern formed by the ANA trench forms an ANA region within the dielectric layer.

公开(公告)号：US20170263506A1

公开(公告)日：2017-09-14

申请号：US15067953

申请日：2016-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Tuhin Guha Neogi ,  Andy Chi-Hung Wei ,  Jia Zeng ,  Jongwook Kye ,  Jason Eugene Stephens ,  Irene Yuh-Ling Lin ,  Sudharshanan Raghunathan ,  Lei Yuan

IPC: H01L21/8238 ,  H01L21/768 ,  G06F17/50 ,  H01L21/027 ,  H01L27/092 ,  H01L23/535 ,  H01L21/8234 ,  H01L21/285

CPC classification number: H01L21/823871 ,  G06F17/5072 ,  H01L21/027 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/535 ,  H01L27/0886 ,  H01L27/0924

Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.

公开(公告)号：US09679809B1

公开(公告)日：2017-06-13

申请号：US15077564

申请日：2016-03-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jongwook Kye ,  Yan Wang ,  Chenchen Wang ,  Wenhui Wang ,  Lei Yuan ,  Jia Zeng ,  Guillaume Bouche

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/28 ,  H01L45/00

CPC classification number: H01L21/28141 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76816 ,  H01L45/1691

Abstract: A method of forming a pattern for interconnect lines in an integrated circuit includes providing a structure having a first lithographic stack, a mandrel layer and a pattern layer disposed over a dielectric stack. Patterning the structure to form mandrels in the mandrel layer and disposing a spacer layer over the mandrels. Etching the spacer layer to form spacers disposed on sidewalls of the mandrels. The spacers and mandrels defining beta and gamma regions. A beta region includes a beta block mask portion and a gamma region includes a gamma block mask portion of the pattern layer. The method also includes etching a beta pillar over the beta block mask portion and etching a gamma pillar over the gamma block mask portion. The method also includes etching the structure to form a pattern in the pattern layer, the pattern including the gamma and beta block mask portions.