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281 条记录 (耗时 0.046 秒)

    Protective seal ring for preventing die-saw induced stress
    37.
    发明授权
    Protective seal ring for preventing die-saw induced stress 有权
    用于防止模锯引起的应力的保护密封环

    公开(公告)号：US08334582B2

    公开(公告)日：2012-12-18

    申请号：US12347026

    申请日：2008-12-31

    申请人： Shin-Puu Jeng ,  Hsien-Wei Chen ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Anbiarshy N. F. Wu ,  Yu-Wen Liu

    发明人： Shin-Puu Jeng ,  Hsien-Wei Chen ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Anbiarshy N. F. Wu ,  Yu-Wen Liu

    IPC分类号： H01L23/544

    CPC分类号： H01L21/78 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor chip includes a semiconductor substrate; a plurality of low-k dielectric layers over the semiconductor substrate; a first passivation layer over the plurality of low-k dielectric layers; and a second passivation layer over the first passivation layer. A first seal ring is adjacent to an edge of the semiconductor chip, wherein the first seal ring has an upper surface substantially level to a bottom surface of the first passivation layer. A second seal ring is adjacent to the first seal ring and on an inner side of the semiconductor chip than the first seal ring. The second seal ring includes a pad ring in the first passivation layer and the second passivation layer. A trench ring includes at least a portion directly over the first seal ring. The trench ring extends from a top surface of the second passivation layer down to at least an interface between the first passivation layer and the second passivation layer.

    摘要翻译： 半导体芯片包括半导体衬底; 半导体衬底上的多个低k电介质层; 在所述多个低k电介质层上的第一钝化层; 以及在所述第一钝化层上的第二钝化层。 第一密封环邻近半导体芯片的边缘，其中第一密封环具有基本上平坦于第一钝化层的底表面的上表面。 第二密封环与第一密封环相邻，并且在半导体芯片的内侧与第一密封环相邻。 第二密封环包括在第一钝化层和第二钝化层中的焊盘环。 沟槽环包括直接在第一密封环上的至少一部分。 沟槽环从第二钝化层的顶表面延伸到至少第一钝化层和第二钝化层之间的界面。

    Structure for improving die saw quality
    38.
    发明授权
    Structure for improving die saw quality 有权
    提高模锯质量的结构

    公开(公告)号：US08278737B2

    公开(公告)日：2012-10-02

    申请号：US12417394

    申请日：2009-04-02

    申请人： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Ying-Ju Chen ,  Yu-Wen Liu ,  Shin-Puu Jeng

    发明人： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Ying-Ju Chen ,  Yu-Wen Liu ,  Shin-Puu Jeng

    IPC分类号： H01L21/00

    CPC分类号： H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device is provided that includes a semiconductor substrate, a plurality of dies formed on the semiconductor substrate, the plurality of dies being separated from one another by a first region extending along a first direction and a second region extending along a second direction different from the first direction, a dummy metal structure formed within a third region that includes a region defined by an intersection of the first region and the second region, a plurality of metal interconnection layers formed over the substrate, and a plurality of dielectric layers formed over the substrate. Each of the metal interconnection layers is disposed within each of the dielectric layers and a dielectric constant of at least one of the dielectric layers is less than about 2.6.

    摘要翻译： 提供了一种半导体器件，其包括半导体衬底，形成在半导体衬底上的多个管芯，所述多个管芯沿着第一方向延伸的第一区域彼此分离，并且沿着不同于第二方向的第二方向延伸的第二区域 第一方向，形成在第三区域内的虚设金属结构，所述第三区域包括由所述第一区域和所述第二区域的交点限定的区域，形成在所述基板上的多个金属互连层，以及形成在所述第二区域上的多个电介质层 基质。 每个金属互连层设置在每个介电层内，并且至少一个电介质层的介电常数小于约2.6。