公开(公告)号：US20180204842A1

公开(公告)日：2018-07-19

申请号：US15574092

申请日：2015-06-23

Applicant: Intel Corporation

Inventor： Elijah V. KARPOV ,  Jack T. KAVALIEROS ,  Robert S. CHAU ,  Niloy MUKHERJEE ,  Rafael RIOS ,  Prashant MAJHI ,  Van H. LE ,  Ravi PILLARISETTY ,  Uday SHAH ,  Gilbert DEWEY ,  Marko RADOSAVLJEVIC

IPC: H01L27/108 ,  H01L27/24 ,  H01L27/11551 ,  H01L27/1156 ,  H01L29/786 ,  H01L45/00 ,  G11C13/00

CPC classification number: H01L27/108 ,  G11C13/0007 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1214 ,  H01L27/2436 ,  H01L27/2472 ,  H01L27/2481 ,  H01L29/7869 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1633

Abstract: A thin film transistor is deposited over a portion of a metal layer over a substrate. A memory element is coupled to the thin film transistor to provide a first memory cell. A second memory cell is over the first memory. A logic block is coupled to at least the first memory cell.

公开(公告)号：US20170229354A1

公开(公告)日：2017-08-10

申请号：US15498280

申请日：2017-04-26

Applicant: Intel Corporation

Inventor： Marko RADOSAVLJEVIC ,  Ravi PILLARISETTY ,  Gilbert DEWEY ,  Niloy MUKHERJEE ,  Jack KAVALIEROS ,  Willy RACHMADY ,  Van LE ,  Benjamin CHU-KUNG ,  Matthew METZ ,  Robert CHAU

IPC: H01L21/84 ,  H01L29/423 ,  H01L29/06 ,  H01L27/12

CPC classification number: H01L21/845 ,  B82Y10/00 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/20 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.

公开(公告)号：US20170186598A1

公开(公告)日：2017-06-29

申请号：US15458897

申请日：2017-03-14

Applicant: Intel Corporation

Inventor： Niti Goel ,  Robert S. CHAU ,  Jack T. KAVALIEROS ,  Benjamin CHU-KUNG ,  Matthew V. METZ ,  Niloy MUKHERJEE ,  Nancy M. ZELICK ,  Gilbert DEWEY ,  Willy RACHMADY ,  Marko RADOSAVLJEVIC ,  Van H. LE ,  Ravi PILLARISETTY ,  Sansaptak DASGUPTA

IPC: H01L21/02 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/20 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L21/0245 ,  H01L21/02381 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02598 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8252 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66795 ,  H01L29/785

Abstract: A single fin or a pair of co-integrated n- and p-type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.

公开(公告)号：US20160343844A1

公开(公告)日：2016-11-24

申请号：US15229079

申请日：2016-08-04

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Robert CHAU ,  Benjamin CHU-KUNG ,  Gilbert DEWEY ,  Jack KAVALIEROS ,  Matthew METZ ,  Niloy MUKHERJEE ,  Ravi PILLARISETTY ,  Marko RADOSAVLJEVIC

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/04 ,  H01L29/10 ,  G06F1/16 ,  H03F3/195 ,  H01L29/66 ,  H01L21/02 ,  G06F1/18 ,  H01L29/20 ,  H03F3/213

CPC classification number: H01L29/7787 ,  G06F1/1633 ,  G06F1/189 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0254 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786 ,  H01L29/7789 ,  H01L29/785 ,  H03F3/195 ,  H03F3/213 ,  H03F2200/451

Abstract: Transistors for high voltage and high frequency operation. A non-planar, polar crystalline semiconductor body having a top surface disposed between first and second opposite sidewalls includes a channel region with a first crystalline semiconductor layer disposed over the first and second sidewalls. The first crystalline semiconductor layer is to provide a two dimensional electron gas (2DEG) within the channel region. A gate structure is disposed over the first crystalline semiconductor layer along at least the second sidewall to modulate the 2DEG. First and second sidewalls of the non-planar polar crystalline semiconductor body may have differing polarity, with the channel proximate to a first of the sidewalls. The gate structure may be along a second of the sidewalls to gate a back barrier. The polar crystalline semiconductor body may be a group III-nitride formed on a silicon substrate with the (1010) plane on a (110) plane of the silicon.

Abstract translation: 用于高压和高频工作的晶体管。 具有设置在第一和第二相对侧壁之间的顶表面的非平面极性晶体半导体本体包括具有设置在第一和第二侧壁上的第一晶体半导体层的沟道区域。 第一晶体半导体层是在沟道区内提供二维电子气（2DEG）。 栅极结构沿至少第二侧壁设置在第一晶体半导体层上方，以调制2DEG。 非平面极性结晶半导体主体的第一和第二侧壁可具有不同的极性，其中通道靠近第一侧壁。 栅极结构可以沿着侧壁中的第二侧面以栅极背栅。 极性结晶半导体体可以是在硅衬底上形成的III族氮化物，其中（1010）面在硅的（110）平面上。

公开(公告)号：US20240128269A1

公开(公告)日：2024-04-18

申请号：US18396360

申请日：2023-12-26

Applicant: Intel Corporation

Inventor： Abhishek A. SHARMA ,  Van H. LE ,  Seung Hoon SUNG ,  Ravi PILLARISETTY ,  Marko RADOSAVLJEVIC

IPC: H01L27/12 ,  G05F1/56 ,  G06F1/26 ,  H01L21/02 ,  H01L21/383 ,  H01L29/24 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/1207 ,  G05F1/56 ,  G06F1/26 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02192 ,  H01L21/02565 ,  H01L21/383 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696 ,  H01L2029/42388

Abstract: Described herein are apparatuses, systems, and methods associated with a voltage regulator circuit that includes one or more thin-film transistors (TFTs). The TFTs may be formed in the back-end of an integrated circuit. Additionally, the TFTs may include one or more unique features, such as a channel layer treated with a gas or plasma, and/or a gate oxide layer that is thicker than in prior TFTs. The one or more TFTs of the voltage regulator circuit may improve the operation of the voltage regulator circuit and free up front-end substrate area for other devices. Other embodiments may be described and claimed.

公开(公告)号：US20220181335A1

公开(公告)日：2022-06-09

申请号：US17673670

申请日：2022-02-16

Applicant: Intel Corporation

Inventor： Abhishek A. SHARMA ,  Brian S. DOYLE ,  Ravi PILLARISETTY ,  Prashant MAJHI ,  Elijah V. KARPOV

IPC: H01L27/1159 ,  G11C11/22 ,  H01L29/51 ,  H01L29/78

Abstract: A ferroelectric field-effect transistor (FeFET) includes first and second gate electrodes, source and drain regions, a semiconductor region between and physically connecting the source and drain regions, a first gate dielectric between the semiconductor region and the first gate electrode, and a second gate dielectric between the semiconductor region and the second gate electrode. The first gate dielectric includes a ferroelectric dielectric. In an embodiment, a memory cell includes this FeFET, with the first gate electrode being electrically connected to a wordline and the drain region being electrically connected to a bitline. In another embodiment, a memory array includes wordlines extending in a first direction, bitlines extending in a second direction, and a plurality of such memory cells at crossing regions of the wordlines and the bitlines. In each memory cell, the wordline is a corresponding one of the wordlines and the bitline is a corresponding one of the bitlines.

公开(公告)号：US20210288049A1

公开(公告)日：2021-09-16

申请号：US17334425

申请日：2021-05-28

Applicant: Intel Corporation

Inventor： Ravi PILLARISETTY ,  Willy RACHMADY ,  Marko RADOSAVLJEVIC ,  Van H. LE ,  Jack T. KAVALIEROS

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238

Abstract: Techniques and mechanisms for operating transistors that are in a stacked configuration. In an embodiment, an integrated circuit (IC) device includes transistors arranged along a line of direction which is orthogonal to a surface of a semiconductor substrate. A first epitaxial structure and a second epitaxial structure are coupled, respectively, to a first channel structure of a first transistor and a second channel structure of a second transistor. The first epitaxial structure and the second epitaxial structure are at different respective levels relative to the surface of the semiconductor substrate. A dielectric material is disposed between the first epitaxial structure and the second epitaxial structure to facilitate electrical insulation of the channels from each other. In another embodiment, the stacked transistors are coupled to provide a complementary metal-oxide-semiconductor (CMOS) inverter circuit.

公开(公告)号：US20200243543A1

公开(公告)日：2020-07-30

申请号：US16635966

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Ravi PILLARISETTY ,  Abhishek A. SHARMA ,  Prashant MAJHI ,  Elijah V. KARPOV ,  Brian S. DOYLE

IPC: H01L27/108 ,  G11C11/4096

Abstract: A memory device comprises a first selector and a storage capacitor in series with the first selector. A second selector is in parallel with the storage capacitor coupled between the first selector and zero volts. A plurality of memory devices form a 2S-1C cross-point DRAM array with 4F2 or less density.

公开(公告)号：US20200098754A1

公开(公告)日：2020-03-26

申请号：US16606702

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Ravi PILLARISETTY ,  Willy RACHMADY ,  Marko RADOSAVLJEVIC ,  Van H. LE ,  Jack T. KAVALIEROS

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238

Abstract: Techniques and mechanisms for operating transistors that are in a stacked configuration. In an embodiment, an integrated circuit (IC) device includes transistors arranged along a line of direction which is orthogonal to a surface of a semiconductor substrate. A first epitaxial structure and a second epitaxial structure are coupled, respectively, to a first channel structure of a first transistor and a second channel structure of a second transistor. The first epitaxial structure and the second epitaxial structure are at different respective levels relative to the surface of the semiconductor substrate. A dielectric material is disposed between the first epitaxial structure and the second epitaxial structure to facilitate electrical insulation of the channels from each other. In another embodiment, the stacked transistors are coupled to provide a complementary metal-oxide-semiconductor (CMOS) inverter circuit.

公开(公告)号：US20200066511A1

公开(公告)日：2020-02-27

申请号：US16113159

申请日：2018-08-27

Applicant: Intel Corporation

Inventor： Ilya KARPOV ,  Brian DOYLE ,  Prashant MAJHI ,  Abhishek SHARMA ,  Ravi PILLARISETTY

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01G4/12 ,  C23C14/08 ,  C23C14/34 ,  C23C14/54

Abstract: Embodiments disclosed herein comprise a ferroelectric material layer and methods of forming such materials. In an embodiment, the ferroelectric material layer comprises hafnium oxide with an orthorhombic phase. In an embodiment, the ferroelectric material layer may also comprise trace elements of a working gas. Additional embodiments may comprise: a semiconductor channel, a source region on a first end of the semiconductor channel, a drain region on a second end of the semiconductor channel, a gate electrode over the semiconductor channel, and a gate dielectric between the gate electrode and the semiconductor channel. In an embodiment, the gate dielectric includes a ferroelectric hafnium oxide. In an embodiment, the hafnium oxide is substantially free from dopants.