公开(公告)号：US20200006388A1

公开(公告)日：2020-01-02

申请号：US16024696

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Patrick MORROW ,  Aaron LILAK ,  Willy RACHMADY ,  Anh PHAN ,  Ehren MANNEBACH ,  Hui Jae YOO ,  Abhishek SHARMA ,  Van H. LE ,  Cheng-Ying HUANG

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/78 ,  H01L21/8258

Abstract: Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a first transistor, an insulator layer above the first transistor, and a second transistor above the insulator layer. The first transistor may be a p-type transistor including a channel in a substrate, a first source electrode, and a first drain electrode. A first metal contact may be coupled to the first source electrode, while a second metal contact may be coupled to the first drain electrode. The insulator layer may be next to the first metal contact, and next to the second metal contact. The second transistor may include a second source electrode, and a second drain electrode. The second source electrode may be coupled to the first metal contact, or the second drain electrode may be coupled to the second metal contact. Other embodiments may be described and/or claimed.

公开(公告)号：US20190393249A1

公开(公告)日：2019-12-26

申请号：US16016387

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Aaron LILAK ,  Justin WEBER ,  Harold KENNEL ,  Willy RACHMADY ,  Gilbert DEWEY ,  Van H. LE ,  Abhishek SHARMA ,  Patrick MORROW

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/78 ,  H01L21/8256

Abstract: Embodiments herein describe techniques for a semiconductor device including a first transistor above a substrate, an insulator layer above the first transistor, and a second transistor above the insulator layer. The first transistor includes a first channel layer above the substrate, and a first gate electrode above the first channel layer. The insulator layer is next to a first source electrode of the first transistor above the first channel layer, next to a first drain electrode of the first transistor above the first channel layer, and above the first gate electrode. The second transistor includes a second channel layer above the insulator layer, and a second gate electrode separated from the second channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20190393223A1

公开(公告)日：2019-12-26

申请号：US16480948

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Van H. LE ,  Gilbert William DEWEY ,  Rafael RIOS ,  Jack T. KAVALIEROS ,  Yih WANG ,  Shriram SHIVARAMAN

IPC: H01L27/108 ,  H01L27/13 ,  G11C11/4096 ,  G11C11/408 ,  H01L29/786 ,  H01L21/768 ,  H01L21/02 ,  H01L29/40 ,  H01L21/311 ,  H01L49/02 ,  H01L29/423 ,  H01L29/66 ,  H01L29/24 ,  H01L29/22

Abstract: A charge storage memory is described based on a vertical shared gate thin-film transistor. In one example, a memory cell structure includes a capacitor to store a charge, the state of the charge representing a stored value, and an access transistor having a drain coupled to a bit line to read the capacitor state, a vertical gate coupled to a word line to write the capacitor state, and a drain coupled to the capacitor to charge the capacitor from the drain through the gate, wherein the gate extends from the word line through metal layers of an integrated circuit.

公开(公告)号：US20180158933A1

公开(公告)日：2018-06-07

申请号：US15576468

申请日：2015-06-27

Applicant: Intel Corporation

Inventor： Van H. LE ,  Gilbert DEWEY ,  Benjamin CHU-KUNG ,  Ashish AGRAWAL ,  Matthew V. METZ ,  Willy RACHMADY ,  Marc C. FRENCH ,  Jack T. KAVALIEROS ,  Rafael RIOS ,  Seiyon KIM ,  Seung Hoon SUNG ,  Sanaz K. GARDNER ,  James M. POWERS ,  Sherry R. TAFT

IPC: H01L29/66 ,  H01L29/786

CPC classification number: H01L29/66977 ,  H01L29/1054 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78609 ,  H01L29/78684 ,  H01L29/78696

Abstract: A method including forming a non-planar conducting channel of a device between junction regions on a substrate, the substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage; and forming a gate stack on the channel, the gate stack including a dielectric material and a gate electrode. A method including forming a buffer material on a semiconductor substrate, the buffer material including a semiconductor material including a different lattice structure than the substrate; forming a blocking material on the buffer material, the blocking material including a property to inhibit carrier leakage; and forming a transistor device on the substrate. An apparatus including a non-planar multi-gate device on a substrate including a transistor device including a channel disposed on a substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage.

公开(公告)号：US20180151684A1

公开(公告)日：2018-05-31

申请号：US15576253

申请日：2015-06-27

Applicant: Intel Corporation

Inventor： Benjamin CHU-KUNG ,  Van H. LE ,  Rafael RIOS ,  Gilbert DEWEY ,  Scott B. CLENDENNING ,  Jack T. KAVALIEROS

IPC: H01L29/45 ,  H01L21/768 ,  H01L21/285 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/45 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76883 ,  H01L23/49827 ,  H01L23/49838 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66568 ,  H01L29/78

Abstract: An apparatus including an integrated circuit device including at least one low density of state metal/semiconductor material interface, wherein the at least one low density of state metal is quantized. An apparatus including an integrated circuit device including at least one interface of a low density of state metal and a semiconductor material, wherein a contact area of the metal at the interface is graded. A method including confining a contact area of a semiconductor material; and forming a metal contact in the contact area.

公开(公告)号：US20180138289A1

公开(公告)日：2018-05-17

申请号：US15576666

申请日：2015-06-27

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Matthew V. METZ ,  Van H. LE ,  Jack T. KAVALIEROS ,  Sanaz K. GARDNER

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/267 ,  H01L27/092

CPC classification number: H01L29/6681 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/30612 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/20 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7853

Abstract: An apparatus including a three-dimensional semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the three-dimensional semiconductor body including a plurality of nanowires including a germanium material disposed in respective planes separated in the junction regions by a second material, wherein a lattice constant of the second material is similar to a lattice constant of the germanium material; and a gate stack disposed on the channel region, the gate stack including a gate electrode disposed on a gate dielectric. A method of including forming a plurality of nanowires in separate planes on a substrate, each of the plurality of nanowires including a germanium material and separated from an adjacent nanowire by a sacrificial material; disposing a gate stack on the plurality of nanowires in a designated channel region, the gate stack including a dielectric material and a gate electrode.

公开(公告)号：US20170154960A1

公开(公告)日：2017-06-01

申请号：US15429126

申请日：2017-02-09

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Van H. LE ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS ,  Robert S. CHAU ,  Seung Hoon SUNG

IPC: H01L29/06 ,  H01L21/306 ,  H01L21/02 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02603 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66613 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858 ,  Y10S977/762 ,  Y10S977/89 ,  Y10S977/938

Abstract: Nanowire-based gate all-around transistor devices having one or more active nanowires and one or more inactive nanowires are described herein. Methods to fabricate such devices are also described. One or more embodiments of the present invention are directed at approaches for varying the gate width of a transistor structure comprising a nanowire stack having a distinct number of nanowires. The approaches include rendering a certain number of nanowires inactive (i.e. so that current does not flow through the nanowire), by severing the channel region, burying the source and drain regions, or both. Overall, the gate width of nanowire-based structures having a plurality of nanowires may be varied by rendering a certain number of nanowires inactive, while maintaining other nanowires as active.

公开(公告)号：US20160276438A1

公开(公告)日：2016-09-22

申请号：US15036406

申请日：2013-12-23

Applicant: INTEL CORPORATION

Inventor： Benjamin CHU-KUNG ,  Sherry R. TAFT ,  Van H. LE ,  Sansaptak DASGUPTA ,  Seung Hoon Hoon SUNG ,  Sanaz K. GARDNER ,  Matthew V. METZ ,  Marko RADOSAVLJEVIC ,  Han Wui THEN

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/161 ,  H01L29/20

CPC classification number: H01L29/1037 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/2003 ,  H01L29/66795

Abstract: Techniques are disclosed for forming a defect-free semiconductor structure on a dissimilar substrate with a multi-aspect ratio mask. The multi-aspect ratio mask comprises a first, second, and third layer formed on a substrate. The second layer has a second opening wider than a first opening and a third opening in the first and third layers, respectively. All three openings are centered along a common central axis. A semiconductor material is grown from the top surface of the substrate and laterally onto the top surface of the first layer within the second opening. The semiconductor material disposed within and vertically below the third opening is etched by using the third layer as an etch mask so that the remaining material that laterally overflowed onto the top surface of the first layer forms a remaining structure.

Abstract translation: 公开了用于在具有多纵横比掩模的不同基板上形成无缺陷半导体结构的技术。 多纵横比掩模包括形成在基板上的第一，第二和第三层。 第二层分别具有比第一和第三层中的第一开口和第三开口更宽的第二开口。 所有三个开口沿着共同的中心轴线居中。 半导体材料从衬底的顶表面生长并横向放置在第二开口内的第一层的顶表面上。 通过使用第三层作为蚀刻掩模来蚀刻设置在第三开口内并垂直于第三开口下方的半导体材料，使得横向溢出到第一层的顶表面上的剩余材料形成剩余结构。

公开(公告)号：US20240128269A1

公开(公告)日：2024-04-18

申请号：US18396360

申请日：2023-12-26

Applicant: Intel Corporation

Inventor： Abhishek A. SHARMA ,  Van H. LE ,  Seung Hoon SUNG ,  Ravi PILLARISETTY ,  Marko RADOSAVLJEVIC

IPC: H01L27/12 ,  G05F1/56 ,  G06F1/26 ,  H01L21/02 ,  H01L21/383 ,  H01L29/24 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/1207 ,  G05F1/56 ,  G06F1/26 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02192 ,  H01L21/02565 ,  H01L21/383 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696 ,  H01L2029/42388

Abstract: Described herein are apparatuses, systems, and methods associated with a voltage regulator circuit that includes one or more thin-film transistors (TFTs). The TFTs may be formed in the back-end of an integrated circuit. Additionally, the TFTs may include one or more unique features, such as a channel layer treated with a gas or plasma, and/or a gate oxide layer that is thicker than in prior TFTs. The one or more TFTs of the voltage regulator circuit may improve the operation of the voltage regulator circuit and free up front-end substrate area for other devices. Other embodiments may be described and claimed.

公开(公告)号：US20220199801A1

公开(公告)日：2022-06-23

申请号：US17132996

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Prashant MAJHI ,  Abhishek A. SHARMA ,  Charles C. KUO ,  Brian S. DOYLE ,  Urusa ALAAN ,  Van H. LE ,  Elijah V. KARPOV ,  Kaan OGUZ ,  Arnab SEN GUPTA

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/49 ,  H01L29/51 ,  H01L21/683 ,  H01L29/78

Abstract: Embodiments disclosed herein include a semiconductor devices with back end of line (BEOL) transistor devices. In an embodiment, a semiconductor device comprises a semiconductor substrate and a BEOL stack over the semiconductor substrate. In an embodiment, a field effect transistor (FET) is embedded in the BEOL stack. In an embodiment, the FET comprises a channel, a gate dielectric over the channel, where the gate dielectric is single crystalline, a gate electrode over the gate dielectric, and a source electrode and a drain electrode passing through the gate dielectric to contact the channel.