中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

122 records (took 0.022 seconds)

    Semiconductor device test apparatuses comprising at least one test site having an array of pockets
    31.
    发明授权
    Semiconductor device test apparatuses comprising at least one test site having an array of pockets 有权

    公开(公告)号：US10481200B2

    公开(公告)日：2019-11-19

    申请号：US16177917

    申请日：2018-11-01

    Applicant: Micron Technology, Inc.

    Inventor： Jaspreet S. Gandhi ,  Michel Koopmans ,  James M. Derderian

    IPC: G01R31/00 ,  G01R31/28 ,  G01R1/073

    Abstract: Apparatus for testing semiconductor devices comprising die stacks, the apparatus comprising a substrate having an array of pockets in a surface thereof arranged to correspond to conductive elements protruding from a semiconductor device to be tested. The pockets include conductive contacts with traces extending to conductive pads, which may be configured as test pads, jumper pads, edge connects or contact pads. The substrate may comprise a semiconductor wafer or wafer segment and, if the latter, multiple segments may be received in recesses in a fixture. Testing may be effected using a probe card, a bond head carrying conductive pins, or through conductors carried by the fixture.

    Uniform back side exposure of through-silicon vias
    33.
    发明授权
    Uniform back side exposure of through-silicon vias 有权

    公开(公告)号：US10410879B2

    公开(公告)日：2019-09-10

    申请号：US15729391

    申请日：2017-10-10

    Applicant: Micron Technology, Inc.

    Inventor： Jaspreet S. Gandhi ,  Wayne H. Huang

    IPC: H01L21/321 ,  H01L21/768

    Abstract: Systems and methods for uniform back side exposure of through-silicon vias (TSVs) are disclosed. In one embodiment, a semiconductor device comprises a substrate having a front side with circuit elements formed thereon, and a back side opposite the front side. A TSV extends between the front side and the back side of the substrate, and a dummy feature is disposed over the back side of the substrate, the dummy feature laterally spaced apart from the TSV and substantially coplanar with the TSV. In another embodiment, a semiconductor device comprises a substrate having a TSV formed therethrough, with a control material disposed over the back side of the substrate, the TSV substantially coplanar with the control material.

    SEMICONDUCTOR DEVICES HAVING CONDUCTIVE VIAS AND METHODS OF FORMING THE SAME
    35.
    发明申请
    SEMICONDUCTOR DEVICES HAVING CONDUCTIVE VIAS AND METHODS OF FORMING THE SAME 审中-公开

    公开(公告)号：US20190229039A1

    公开(公告)日：2019-07-25

    申请号：US16371635

    申请日：2019-04-01

    Applicant: Micron Technology, Inc.

    Inventor： Jaspreet S. Gandhi

    IPC: H01L23/48 ,  H01L23/532 ,  H01L21/768

    Abstract: Semiconductor devices having a conductive via and methods of forming the same are described herein. As an example, a semiconductor devices may include a conductive via formed in a substrate material, a barrier material, a first dielectric material on the barrier material, a coupling material formed on the substrate material and on at least a portion of the dielectric material, a second dielectric material formed on the coupling material, and an interconnect formed on the conductive via.

    Thermal pads between stacked semiconductor dies and associated systems and methods
    38.
    发明授权
    Thermal pads between stacked semiconductor dies and associated systems and methods 有权

    公开(公告)号：US10096579B2

    公开(公告)日：2018-10-09

    申请号：US15683336

    申请日：2017-08-22

    Applicant: Micron Technology, Inc.

    Inventor： Jaspreet S. Gandhi ,  Michel Koopmans

    IPC: H01L21/00 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

    Abstract: Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures.

    Uniform back side exposure of through-silicon vias
    40.
    发明授权
    Uniform back side exposure of through-silicon vias 有权

    公开(公告)号：US09818622B2

    公开(公告)日：2017-11-14

    申请号：US14608751

    申请日：2015-01-29

    Applicant: Micron Technology, Inc.

    Inventor： Jaspreet S. Gandhi ,  Wayne H. Huang

    IPC: H01L23/48 ,  H01L21/288 ,  H01L21/768 ,  H01L21/321 ,  H01L23/532 ,  H01L23/528

    CPC classification number: H01L21/3212 ,  H01L21/7684 ,  H01L21/76898

    Abstract: Systems and methods for uniform back side exposure of through-silicon vias (TSVs) are disclosed. In one embodiment, a semiconductor device comprises a substrate having a front side with circuit elements formed thereon, and a back side opposite the front side. A TSV extends between the front side and the back side of the substrate, and a dummy feature is disposed over the back side of the substrate, the dummy feature laterally spaced apart from the TSV and substantially coplanar with the TSV. In another embodiment, a semiconductor device comprises a substrate having a TSV formed therethrough, with a control material disposed over the back side of the substrate, the TSV substantially coplanar with the control material.

Patent Agency Ranking