公开(公告)号：US09899303B2

公开(公告)日：2018-02-20

申请号：US14862457

申请日：2015-09-23

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Chun-Tang Lin ,  Mu-Hsuan Chan ,  Chieh-Yuan Chi

IPC: H01L23/49 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49811 ,  H01L21/486 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/18162

Abstract: A method for fabricating an electronic package is provided, which includes the steps of: providing an insulating layer having at least an electronic element embedded therein; forming at least a first via hole on one side of the insulating layer; forming a first conductor in the first via hole of the insulating layer; forming on the insulating layer a first circuit structure electrically connected to the electronic element and the first conductor; and forming a second via hole on the other side of the insulating layer, wherein the second via hole communicates with the first via hole. As such, the second via hole and the first via hole constitute a through hole. Since the through hole is fabricated through two steps, the aspect ratio (depth/width) of the through hole can be adjusted according to the practical need so as to improve the process yield.

公开(公告)号：US20170309579A1

公开(公告)日：2017-10-26

申请号：US15494034

申请日：2017-04-21

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Po-Hao Wang ,  Chang-Fu Lin ,  Chun-Tang Lin ,  Bo-Hao Chang

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31

Abstract: Provided is a substrate structure, including a substrate having at least one chamfer formed on a surface thereof, and a plurality of conductive bodies formed to the substrate. Therefore, a stress generated during the packaging process is alleviated through the chamfer, and the substrate structure is prevented from being cracked. An electronic package employing the substrate structure is also provided.

公开(公告)号：US09607941B2

公开(公告)日：2017-03-28

申请号：US14669527

申请日：2015-03-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Chun-Tang Lin ,  Chieh-Yuan Chi ,  Mu-Hsuan Chan

IPC: H01L21/768 ,  H01L23/31 ,  H01L23/532 ,  H01L23/522 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76879 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/53228 ,  H01L23/5389 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a conductive via structure is provided, which includes the steps of: forming in an encapsulant a plurality of openings penetrating therethrough; forming a dielectric layer on the encapsulant and in the openings of the encapsulant; forming a plurality of vias in the dielectric layer in the openings of the encapsulant; and forming a conductive material in the vias to thereby form conductive vias. Therefore, by filling the openings having rough wall surfaces with the dielectric layer so as to form the vias having even wall surfaces, the present invention improves the quality of the conductive vias.

公开(公告)号：US09349705B2

公开(公告)日：2016-05-24

申请号：US14616078

申请日：2015-02-06

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chien-Feng Chan ,  Mu-Hsuan Chan ,  Chun-Tang Lin ,  Yi-Che Lai

IPC: H01L21/4763 ,  H01L23/00 ,  H01L23/488 ,  H01L21/441 ,  H01L21/56 ,  H01L23/14

CPC classification number: H01L24/81 ,  H01L21/441 ,  H01L21/56 ,  H01L23/145 ,  H01L23/147 ,  H01L23/488 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/05572 ,  H01L2224/13022 ,  H01L2224/13084 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2224/83104 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: A conductive bump structure used to be formed on a substrate having a plurality of bonding pads. The conductive bump structure includes a first metal layer formed on the bonding pads, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The second metal layer has a second melting point higher than a third melting point of the third metal layer. Therefore, a thermal compression bonding process is allowed to be performed to the third metal layer first so as to bond the substrate to another substrate, and then a reflow process can be performed to melt the second metal layer and the third metal layer into each other so as to form an alloy portion, thus avoiding cracking of the substrate.

Abstract translation: 用于形成在具有多个接合焊盘的基板上的导电凸块结构。 导电凸块结构包括在接合焊盘上形成的第一金属层，形成在第一金属层上的第二金属层和形成在第二金属层上的第三金属层。 第二金属层的第二熔点高于第三金属层的第三熔点。 因此，首先对第三金属层进行热压接，从而将基板粘合到另一基板上，然后进行回流处理，使第二金属层和第三金属层彼此熔融 从而形成合金部分，从而避免基板的开裂。

公开(公告)号：US20160079110A1

公开(公告)日：2016-03-17

申请号：US14849639

申请日：2015-09-10

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Kuan-Wei Chuang ,  Shih-Kuang Chiu ,  Chun-Tang Lin ,  Jung-Pang Huang

IPC: H01L21/683 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/528

CPC classification number: H01L21/6835 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/528 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/18162

Abstract: A semiconductor package is provided, which includes: a carrier; a frame having a plurality of openings, wherein the frame is bonded to the carrier and made of a material different from that of the carrier; a plurality of electronic elements disposed in the openings of the frame, respectively; an encapsulant formed in the openings of the frame for encapsulating the electronic elements; and a circuit layer formed on and electrically connected to the electronic elements. By accurately controlling the size of the openings of the frame, the present invention increases the accuracy of positioning of the electronic elements so as to improve the product yield in subsequent processes.

Abstract translation: 提供一种半导体封装，其包括：载体; 具有多个开口的框架，其中所述框架结合到所述载体并且由与所述载体的材料不同的材料制成; 分别设置在框架的开口中的多个电子元件; 形成在框架的开口中的密封剂，用于封装电子元件; 以及形成在电子元件上并电连接到电子元件的电路层。 通过精确地控制框架的开口的尺寸，本发明提高了电子元件的定位精度，从而提高后续处理中的产品产量。

公开(公告)号：US09269693B2

公开(公告)日：2016-02-23

申请号：US14604128

申请日：2015-01-23

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chien-Feng Chan ,  Chun-Tang Lin ,  Yi-Che Lai

IPC: H01L33/06 ,  H01L23/00 ,  H01L23/498 ,  H01L49/02 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L24/94 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L28/00 ,  H01L2224/0231 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/18161 ,  H01L2924/19103 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor chip having opposite first and second surfaces; an RDL structure formed on the first surface of the semiconductor chip and having opposite third and fourth surfaces and a plurality of first conductive through holes penetrating the third and fourth surfaces thereof, wherein the RDL structure is formed on the semiconductor chip through the fourth surface thereof and electrically connected to the semiconductor chip through a plurality of first conductive elements, and the third surface of the RDL structure has a redistribution layer formed thereon; a plurality of conductive bumps formed on the redistribution layer; and an encapsulant formed on the first surface of the semiconductor chip for encapsulating the RDL structure, wherein the conductive bumps are embedded in and exposed from the encapsulant. The invention effectively prevents warpage of the semiconductor package and improves the electrical connection significantly.

Abstract translation: 提供半导体封装。 半导体封装包括具有相反的第一和第二表面的半导体芯片; 形成在半导体芯片的第一表面上并且具有相反的第三和第四表面的RDL结构以及穿过其第三和第四表面的多个第一导电通孔，其中RDL结构通过其第四表面形成在半导体芯片上 并通过多个第一导电元件与半导体芯片电连接，并且RDL结构的第三表面在其上形成再分布层; 形成在再分配层上的多个导电凸块; 以及密封剂，其形成在所述半导体芯片的用于封装所述RDL结构的所述第一表面上，其中所述导电凸块嵌入并暴露于所述密封剂。 本发明有效地防止了半导体封装的翘曲，并显着地改善了电连接。

公开(公告)号：US20160013146A1

公开(公告)日：2016-01-14

申请号：US14736436

申请日：2015-06-11

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Mu-Hsuan Chan ,  Chieh-Yuan Chi ,  Chun-Tang Lin

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/19 ,  H01L21/568 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/014 ,  H01L2924/18162

Abstract: A method for fabricating a package structure is provided, including the steps of: sequentially forming a metal layer and a dielectric layer on a first carrier, wherein the dielectric layer has a plurality of openings exposing portions of the metal layer; disposing an electronic element on the dielectric layer via an active surface thereof and mounting a plurality of conductive elements of metal balls on the exposed portions of the metal layer; forming an encapsulant on the dielectric layer for encapsulating the electronic element and the conductive elements; removing the first carrier; and patterning the metal layer into first circuits and forming second circuits on the dielectric layer, wherein the second circuits are electrically connected to the electronic element and the first circuits. The invention dispenses with the conventional laser ablation process so as to simplify the fabrication process, save the fabrication cost and increase the product reliability.

Abstract translation: 提供了一种制造封装结构的方法，包括以下步骤：在第一载体上依次形成金属层和电介质层，其中电介质层具有暴露金属层部分的多个开口; 将电子元件经由其活性表面设置在电介质层上，并将金属球的多个导电元件安装在金属层的暴露部分上; 在所述电介质层上形成密封剂以封装所述电子元件和所述导电元件; 移除第一载体; 以及将所述金属层图案化成第一电路并在所述电介质层上形成第二电路，其中所述第二电路电连接到所述电子元件和所述第一电路。 本发明省去了常规的激光烧蚀工艺，以简化制造工艺，节省制造成本并提高产品的可靠性。

公开(公告)号：US09147668B2

公开(公告)日：2015-09-29

申请号：US14074165

申请日：2013-11-07

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chi-Tung Yeh ,  Chun-Tang Lin

IPC: H01L23/00

CPC classification number: H01L24/82 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/01 ,  H01L24/02 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L24/94 ,  H01L24/95 ,  H01L24/97 ,  H01L24/98 ,  H01L2221/68318 ,  H01L2221/68331 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2224/83005 ,  H01L2224/831 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83

Abstract: A method for fabricating a semiconductor structure is disclosed. First, an interposer is disposed on a carrier. The carrier has a base body and a bonding layer bonded to the base body. The interposer has opposite first and second sides and the first side has a plurality of conductive elements. The interposer is disposed on the carrier with the first side bonded to the bonding layer and the conductive elements embedded in the bonding layer. Then, at least a semiconductor element is disposed on the second side of the interposer. As such, the semiconductor element and the interposer form a semiconductor structure. Since the conductive elements are embedded in the bonding layer instead of the base body, the present invention eliminates the need to form concave portions in the base body for receiving the conductive elements. Therefore, the method of the present invention is applicable to interposers of different specifications.

Abstract translation: 公开了一种制造半导体结构的方法。 首先，将载体放置在载体上。 载体具有结合到基体的基体和结合层。 插入器具有相对的第一和第二侧，并且第一侧具有多个导电元件。 插入器设置在载体上，其第一面接合到接合层，并且导电元件嵌入在接合层中。 然后，至少一个半导体元件设置在插入件的第二侧上。 因此，半导体元件和插入件形成半导体结构。 由于导电元件被嵌入接合层而不是基体中，所以本发明不需要在基体中形成用于接收导电元件的凹部。 因此，本发明的方法可应用于不同规格的插入件。

公开(公告)号：US08987012B2

公开(公告)日：2015-03-24

申请号：US13845698

申请日：2013-03-18

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Pin-Cheng Huang ,  Chun-Tang Lin ,  Wen-Tsung Tseng ,  Yi-Che Lai

IPC: H01L21/66

CPC classification number: H01L22/14 ,  H01L21/6836 ,  H01L22/20 ,  H01L23/147 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L2221/68331 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/16195 ,  H01L2924/351 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/81

Abstract: A method of testing a semiconductor package is provided, including: disposing at least an interposer on a top surface of an adhesive layer, the interposer having a first surface and a second surface opposite to the first surface, a plurality of conductive elements disposed between the second surface of the interposer and the adhesive layer; disposing at least a semiconductor chip on the first surface of the interposer, and performing an electrical test on the semiconductor chip via the conductive elements, wherein if there are a plurality of semiconductor chips that are disposed on the first surface of the interposer, the step of disposing the semiconductor chip and performing the electrical test on the semiconductor chip is iterated; and removing the adhesive layer. By using the method, the fabrication cost and equipment cost of the semiconductor package are reduced, and product yield is increased.

Abstract translation: 提供了一种测试半导体封装的方法，包括：至少在粘合剂层的顶表面上设置插入件，所述插入件具有第一表面和与第一表面相对的第二表面，多个导电元件设置在第二表面之间 插入器的第二表面和粘合剂层; 在所述插入件的第一表面上设置至少一个半导体芯片，并且经由所述导电元件对所述半导体芯片进行电测试，其中如果存在设置在所述插入件的第一表面上的多个半导体芯片，则所述步骤 重复设置半导体芯片并对半导体芯片进行电气测试; 并去除粘合剂层。 通过使用该方法，半导体封装的制造成本和设备成本降低，产品产量增加。

公开(公告)号：US20140027926A1

公开(公告)日：2014-01-30

申请号：US13872468

申请日：2013-04-29

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Wang-Ting Chen ,  Mu-Hsuan Chan ,  Yi-Chian Liao ,  Chun-Tang Lin ,  Yi-Che Lai

IPC: H01L23/28 ,  H01L23/538 ,  H01L21/56

CPC classification number: H01L21/561 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L21/78 ,  H01L23/28 ,  H01L23/31 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5384 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/10253 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/81

Abstract: A semiconductor package is provided, including: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top side of the interposer; a semiconductor element disposed on the top side of the interposer; and an adhesive formed between the interposer and the semiconductor element. By encapsulating the interposer with the encapsulant, warpage of the interposer is avoided and a planar surface is provided for the semiconductor element to be disposed thereon, thereby improving the reliability of electrical connection between the interposer and the semiconductor element.

Abstract translation: 提供半导体封装，包括：载体; 至少设置在所述载体上的插入件; 形成在所述载体上的密封剂，用于在暴露所述插入件的顶侧的同时封装所述插入件; 设置在所述插入件的顶侧的半导体元件; 以及形成在插入件和半导体元件之间的粘合剂。 通过用封装剂封装插入件，避免了插入器的翘曲，并且为了将半导体元件设置在其上提供平坦的表面，从而提高了插入件与半导体元件之间的电连接的可靠性。