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公开(公告)号：US09508769B1
公开(公告)日：2016-11-29
申请号：US15012288
申请日：2016-02-01
发明人： Sheng-Chan Li , Chih-Hui Huang , Cheng-Yuan Tsai , Yeur-Luen Tu
IPC分类号： H01L27/146 , H01L21/762 , H01L21/768
CPC分类号： H01L27/1463 , H01L21/762 , H01L21/76224 , H01L21/76898 , H01L27/1462 , H01L27/14621 , H01L27/14623 , H01L27/14629 , H01L27/1464 , H01L27/14685 , H01L27/14689
摘要： Some embodiments of the present disclosure provide a semiconductor structure comprising: a substrate, a radiation-sensing region in the substrate, and a trench in the substrate including a liner over an inner wall of the trench, a FSG layer over the line, an oxide layer over the FSG layer, and a reflective material over the oxide layer. The radiation-sensing region of the semiconductor structure comprises a plurality of radiation-sensing units. The trench of the semiconductor structure separates at least two of the radiation-sensing units. The FSG layer of the semiconductor structure comprises at least 2 atomic percent free fluorine and a thickness of from about 500 to about 1300 angstroms.
摘要翻译： 本公开的一些实施例提供一种半导体结构，包括：衬底，衬底中的辐射感测区域和衬底中的沟槽，其包括在沟槽的内壁上的衬垫，该线上的FSG层，氧化物 层，并且在氧化物层上方具有反射材料。 半导体结构的辐射感测区域包括多个辐射感测单元。 半导体结构的沟槽分离至少两个辐射感测单元。 半导体结构的FSG层包含至少2原子％的游离氟和约500至约1300埃的厚度。
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公开(公告)号：US09490158B2
公开(公告)日：2016-11-08
申请号：US14592788
申请日：2015-01-08
发明人： Chih-Hui Huang , Yen-Chang Chu , Kuan-Liang Liu , Ping-Yin Liu , Cheng-Yuan Tsai , Yeur-Luen Tu , Chia-Shiung Tsai , Ru-Liang Lee
IPC分类号： H01L21/687 , H01L21/67 , H01L21/683
CPC分类号： H01L21/68785 , B32B37/1018 , B32B2457/14 , H01L21/67092 , H01L21/68 , H01L21/6838 , H01L21/68735 , H01L24/75 , H01L2224/757 , H01L2224/75983
摘要： A bonding chuck is discussed with methods of using the bonding chuck and tools including the bonding chuck. A method includes loading a first wafer on first surface of a first bonding chuck, loading a second wafer on a second bonding chuck, and bonding the first wafer to the second wafer. The first surface is defined at least in part by a first portion of a first spherical surface and a second portion of a second spherical surface. The first spherical surface has a first radius, and the second spherical surface has a second radius. The first radius is less than the second radius.
摘要翻译： 讨论了使用粘合卡盘和包括粘合卡盘的工具的方法的粘合卡盘。 一种方法包括将第一晶片装载在第一接合卡盘的第一表面上，将第二晶片装载在第二接合卡盘上，以及将第一晶片接合到第二晶片。 第一表面至少部分地由第一球形表面的第一部分和第二球形表面的第二部分限定。 第一球面具有第一半径，第二球面具有第二半径。 第一个半径小于第二个半径。
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33.发明授权公开(公告)号：US09425240B2
公开(公告)日：2016-08-23
申请号：US14012713
申请日：2013-08-28
IPC分类号： H01L29/08 , H01L27/30 , H01L27/146
CPC分类号： H01L27/307 , H01L27/14621 , H01L27/14627 , H01L27/14665 , H01L51/107
摘要： Embodiments of forming an image sensor with organic photodiodes are provided. Trenches are formed in the organic photodiodes to increase the PN-junction interfacial area, which improves the quantum efficiency (QE) of the photodiodes. The organic P-type material is applied in liquid form to fill the trenches. A mixture of P-type materials with different work function values and thickness can be used to meet the desired work function value for the photodiodes.
摘要翻译： 提供了用有机光电二极管形成图像传感器的实施例。 在有机光电二极管中形成沟槽以增加PN结界面积，这提高了光电二极管的量子效率（QE）。 有机P型材料以液体形式施加以填充沟槽。 可以使用具有不同功函数值和厚度的P型材料的混合物来满足光电二极管的期望功函数值。
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34.发明申请公开(公告)号：US20160049384A1
公开(公告)日：2016-02-18
申请号：US14459144
申请日：2014-08-13
发明人： Chen-Fa Lu , Cheng-Yuan Tsai , Yeur-Luen Tu , Chia-Shiung Tsai
IPC分类号： H01L25/065 , H01L21/768 , H01L23/528 , H01L23/522 , H01L25/00 , H01L23/00
CPC分类号： H01L25/0657 , H01L21/76805 , H01L21/76877 , H01L21/76898 , H01L21/8221 , H01L23/293 , H01L23/3114 , H01L23/3192 , H01L23/481 , H01L23/5226 , H01L23/528 , H01L23/562 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/09 , H01L24/13 , H01L24/80 , H01L24/89 , H01L25/50 , H01L27/0688 , H01L2224/023 , H01L2224/02351 , H01L2224/024 , H01L2224/0345 , H01L2224/0401 , H01L2224/05008 , H01L2224/05024 , H01L2224/05025 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05572 , H01L2224/0558 , H01L2224/05644 , H01L2224/05647 , H01L2224/08145 , H01L2224/08146 , H01L2224/1132 , H01L2224/1145 , H01L2224/11462 , H01L2224/11849 , H01L2224/12105 , H01L2224/13024 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/80895 , H01L2224/80896 , H01L2224/9202 , H01L2224/9212 , H01L2225/06548 , H01L2224/03 , H01L2224/11 , H01L2924/00014 , H01L2924/01029 , H01L2924/014 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82 , H01L2924/01074
摘要： A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on a first side of the second semiconductor substrate. The first substrate is bonded to the second substrate at a bonding interface. A via extends at least through the second semiconductor substrate into the second interconnect structure. The first stress buffer layer is on a second side of the second semiconductor substrate opposite from the first side of the second semiconductor substrate. The PPI structure is on the first stress buffer layer and is electrically coupled to the via. The second stress buffer layer is on the PPI structure and the first stress buffer layer.
摘要翻译： 结构包括第一和第二衬底，第一和第二应力缓冲层以及后钝化互连（PPI）结构。 第一和第二衬底分别包括第一和第二半导体衬底以及第一和第二半导体衬底上的第一和第二互连结构。 第二互连结构位于第二半导体衬底的第一侧上。 第一衬底在接合界面处结合到第二衬底。 通孔至少通过第二半导体衬底延伸到第二互连结构中。 第一应力缓冲层位于与第二半导体衬底的第一侧相反的第二半导体衬底的第二侧上。 PPI结构位于第一应力缓冲层上，并电连接到通孔。 第二应力缓冲层位于PPI结构和第一应力缓冲层上。
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公开(公告)号：US09263595B2
公开(公告)日：2016-02-16
申请号：US13948998
申请日：2013-07-23
发明人： Chih-Wei Lin , Yi-Fang Lee , Cheng-Ta Wu , Cheng-Yuan Tsai
IPC分类号： H01L29/788 , H01L21/28 , H01L27/115 , H01L29/423 , H01L29/51
CPC分类号： H01L29/788 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/513 , H01L29/7881
摘要： Non-volatile memories and methods of fabrication thereof are described. In one embodiment, a method of fabricating a semiconductor device includes forming an oxide layer over a semiconductor substrate, and exposing the oxide layer to a first nitridation step to form a first nitrogen rich region. The first nitrogen rich region is disposed adjacent an interface between the oxide layer and the semiconductor substrate. After the first nitridation step, the oxide layer is exposed to a second nitridation step to form a second nitrogen rich region. A first gate electrode is formed on the oxide layer, wherein the second nitrogen rich region is disposed adjacent an interface between the oxide layer and the first gate electrode.
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公开(公告)号：US12021113B2
公开(公告)日：2024-06-25
申请号：US17574030
申请日：2022-01-12
发明人： Hsing-Lien Lin , Jui-Lin Chu , Cheng-Yuan Tsai
IPC分类号： H01L49/02
CPC分类号： H01L28/60
摘要： Various embodiments of the present disclosure are directed towards an amorphous bottom electrode structure (BES) for a metal-insulator-metal (MIM) capacitor. The MIM capacitor comprises a bottom electrode, an insulator layer overlying the bottom electrode, and a top electrode overlying the insulator layer. The bottom electrode comprises a crystalline BES and the amorphous BES, and the amorphous BES overlies the crystalline BES and forms a top surface of the bottom electrode. Because the amorphous BES is amorphous, instead of crystalline, a top surface of the amorphous BES may have a small roughness compared to that of the crystalline BES. Because the amorphous BES forms the top surface of the bottom electrode, the top surface of the bottom electrode may have a small roughness compared to what it would otherwise have if the crystalline BES formed the top surface. The small roughness may improve a lifespan of the MIM capacitor.
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公开(公告)号：US20240203472A1
公开(公告)日：2024-06-20
申请号：US18589540
申请日：2024-02-28
CPC分类号： G11C11/161 , G11C11/1657 , G11C11/1659 , G11C11/5614 , G11C11/5657 , G11C11/5678 , H10B53/30 , H10B61/22 , H10B63/30
摘要： Various embodiments of the present disclosure are directed towards a memory device. The memory device has a first transistor having a first source/drain and a second source/drain, where the first source/drain and the second source/drain are disposed in a semiconductor substrate. A dielectric structure is disposed over the semiconductor substrate. A first memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the first memory cell has a first electrode and a second electrode, where the first electrode of the first memory cell is electrically coupled to the first source/drain of the first transistor. A second memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the second memory cell has a first electrode and a second electrode, where the first electrode of the second memory cell is electrically coupled to the second source/drain of the first transistor.
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公开(公告)号：US20240023344A1
公开(公告)日：2024-01-18
申请号：US18359308
申请日：2023-07-26
发明人： Bi-Shen Lee , Yi Yang Wei , Hai-Dang Trinh , Hsun-Chung Kuang , Cheng-Yuan Tsai
IPC分类号： H10B53/30
摘要： In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a lower electrode structure disposed over one or more interconnects. The one or more interconnects are arranged within a lower inter-level dielectric (ILD) structure over a substrate. A barrier is arranged along a lower surface of the lower electrode structure. The barrier separates the lower electrode structure from the one or more interconnects. An amorphous initiation layer is over the lower electrode layer and a ferroelectric material is on the amorphous initiation layer. The ferroelectric material has a substantially uniform orthorhombic crystalline phase. An upper electrode is over the ferroelectric material.
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公开(公告)号：US11778931B2
公开(公告)日：2023-10-03
申请号：US17868824
申请日：2022-07-20
CPC分类号： H10N70/828 , H10B63/30 , H10N70/041 , H10N70/063 , H10N70/245 , H10N70/826 , H10N70/8416
摘要： Some embodiments relate to a method for forming an integrated chip. The method includes forming a bottom electrode over a substrate. A data storage layer is formed on the bottom electrode. A diffusion barrier layer is formed over the data storage layer. The diffusion barrier layer has a first diffusion activation temperature. A top electrode is formed over the diffusion barrier layer. The top electrode has a second diffusion activation temperature less than the first diffusion activation temperature.
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公开(公告)号：US20230187294A1
公开(公告)日：2023-06-15
申请号：US17699717
申请日：2022-03-21
发明人： Ming-Che Lee , Kuo-Ming Wu , Sheng-Chau Chen , Hau-Yi Hsiao , Guanyu Luo , Ping-Tzu Chen , Cheng-Yuan Tsai
IPC分类号： H01L23/18 , H01L23/522 , H01L23/00 , H01L21/3105 , H01L25/00
CPC分类号： H01L23/18 , H01L23/5226 , H01L23/562 , H01L21/31051 , H01L24/80 , H01L25/50 , H01L2224/80001 , H01L25/0657
摘要： The present disclosure relates to a semiconductor wafer structure including a semiconductor substrate and a plurality of semiconductor devices disposed along the semiconductor substrate. A dielectric stack including a plurality of dielectric layers is arranged over the semiconductor substrate. A conductive interconnect structure is within the dielectric stack. A seal ring layer is over the dielectric stack and laterally surrounds the dielectric stack along a first sidewall of the dielectric stack. The seal ring layer includes a first protrusion that extends into a first trench in the semiconductor substrate.
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