公开(公告)号：US08492878B2

公开(公告)日：2013-07-23

申请号：US12840688

申请日：2010-07-21

申请人： Mukta G. Farooq ,  Robert Hannon ,  Richard P. Volant

发明人： Mukta G. Farooq ,  Robert Hannon ,  Richard P. Volant

IPC分类号： H01L29/40

CPC分类号： H01L21/76898 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/93 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/11002 ,  H01L2224/11334 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81801 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/15788 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2224/05552

摘要： A through-substrate via (TSV) structure that is immune to metal contamination due to a backside planarization process is provided. After forming a through-substrate via (TSV) trench, a diffusion barrier liner is conformally deposited on the sidewalls of the TSV trench. A dielectric liner is formed by depositing a dielectric material on vertical portions of the diffusion barrier liner. A metallic conductive via structure is formed by subsequently filling the TSV trench. Horizontal portions of the diffusion barrier liner are removed. The diffusion barrier liner protects the semiconductor material of the substrate during the backside planarization by blocking residual metallic material originating from the metallic conductive via structure from entering into the semiconductor material of the substrate, thereby protecting the semiconductor devices within the substrate from metallic contamination.

摘要翻译： 提供了由于背面平坦化处理而对金属污染免疫的贯穿衬底通孔（TSV）结构。 在形成贯穿衬底通孔（TSV）沟槽之后，扩散阻挡衬里共形沉积在TSV沟槽的侧壁上。 通过在扩散阻挡衬里的垂直部分上沉积介电材料形成电介质衬垫。 通过随后填充TSV沟槽形成金属导电通孔结构。 去除扩散阻挡衬里的水平部分。 扩散阻挡衬里通过阻挡源自金属导电通路结构的残余金属材料进入衬底的半导体材料来保护衬底的半导体材料，从而保护衬底内的半导体器件免受金属污染。

公开(公告)号：US20120315753A1

公开(公告)日：2012-12-13

申请号：US13154905

申请日：2011-06-07

申请人： Mukta G. Farooq ,  Troy Lawrence Graves-Abe

发明人： Mukta G. Farooq ,  Troy Lawrence Graves-Abe

IPC分类号： H01L21/283

CPC分类号： H01L21/76898 ,  H01L21/2885 ,  H01L21/306 ,  H01L21/6835 ,  H01L21/76841 ,  H01L21/76846 ,  H01L21/76879 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/1084 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/00012 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

摘要： A method for fabricating through-silicon vias (TSVs) for semiconductor devices is provided. Specifically, the method involves utilizing copper contact pads in a back-end-of-line wiring level, wherein the copper contact pads act as cathodes for performing an electroplating technique to fill TSVs with plated-conductive material (e.g., copper) from an electroplating solution. Moreover, the method provides a way to fill high aspect ratio TSVs with minimal additional semiconductor fabrication process steps, which can increase the silicon area that is available for forming additional electronic components on integrated circuits.

摘要翻译： 提供了一种用于制造用于半导体器件的硅通孔（TSV）的方法。 具体地，该方法包括在后端线路布线层中利用铜接触焊盘，其中铜接触焊盘用作执行电镀技术的阴极，用电镀导电材料（例如铜）填充TSV 解。 此外，该方法提供了通过最小的附加半导体制造工艺步骤填充高纵横比TSV的方法，其可以增加可用于在集成电路上形成附加电子部件的硅面积。

公开(公告)号：US20120199975A1

公开(公告)日：2012-08-09

申请号：US13023743

申请日：2011-02-09

申请人： Mukta G. Farooq ,  John A. Griesemer ,  Gary LaFontant ,  William Francis Landers ,  Timothy Dooling Sullivan

发明人： Mukta G. Farooq ,  John A. Griesemer ,  Gary LaFontant ,  William Francis Landers ,  Timothy Dooling Sullivan

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： The embodiments provide a method for reducing electromigration in a circuit containing a through-silicon via (TSV) and the resulting novel structure for the TSV. A TSV is formed through a semiconductor substrate. A first end of the TSV connects to a first metallization layer on a device side of the semiconductor substrate. A second end of the TSV connects to a second metallization layer on a grind side of the semiconductor substrate. A first flat edge is created on the first end of the TSV at the intersection of the first end of the TSV and the first metallization layer. A second flat edge is created on the second end of the TSV at the intersection of the second end of the TSV and the second metallization layer. On top of the first end a metal contact grid is placed, having less than eighty percent metal coverage.

公开(公告)号：US20120168952A1

公开(公告)日：2012-07-05

申请号：US13418261

申请日：2012-03-12

申请人： Mukta G. Farooq ,  Emily R. Kinser ,  Ian D. Melville ,  Krystyna W. Semkow

发明人： Mukta G. Farooq ,  Emily R. Kinser ,  Ian D. Melville ,  Krystyna W. Semkow

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L21/02697 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05007 ,  H01L2224/05016 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05187 ,  H01L2224/05562 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/15787 ,  H01L2924/04953 ,  H01L2924/01014 ,  H01L2224/05552 ,  H01L2924/00

摘要： Disclosed is a process of making a semiconductor device wherein an insulation layer has a copper plug in contact with the last wiring layer of the device. There may also be a barrier layer separating the copper plug from the insulation layer. There may also be a cap layer over the copper plug to protect it from oxidation. There may also be a dielectric layer over the cap layer.

摘要翻译： 公开了制造半导体器件的方法，其中绝缘层具有与器件的最后布线层接触的铜插塞。 还可以存在将铜塞与绝缘层分离的阻挡层。 在铜塞上方也可能有一个盖层，以防止它被氧化。 在盖层上还可以存在介电层。

公开(公告)号：US08039964B2

公开(公告)日：2011-10-18

申请号：US12038241

申请日：2008-02-27

申请人： Mukta G. Farooq ,  Emily R. Kinser

发明人： Mukta G. Farooq ,  Emily R. Kinser

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/76831 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76829 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05666 ,  H01L2224/11 ,  H01L2224/13006 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/00014

摘要： A line trough and a via cavity are formed within a dielectric layer comprising a fluorosilicate glass (FSG) layer. A fluorine depleted adhesion layer is formed within the line trough and the via cavity either by a plasma treatment that removes fluorine from exposed surfaces of the FSG layer, or by deposition of a substantially fluorine-free dielectric layer. Metal is deposited within the line trough and the via cavity to form a metal line and a metal via. The fluorine depleted adhesion layer provides enhanced adhesion to the metal line compared with prior art structures in which a metal line directly contacts a FSG layer. The enhanced adhesion of metal with an underlying dielectric layer provides higher resistance to delamination for a semiconductor package employing lead-free C4 balls on a metal interconnect structure.

摘要翻译： 在包含氟硅酸盐玻璃（FSG）层的电介质层内形成线槽和通孔。 通过从FSG层的暴露表面除去氟的等离子体处理或通过沉积基本上无氟的介电层，在管线槽和通孔内形成氟贫化粘合层。 金属沉积在管线槽和通孔腔内以形成金属线和金属通孔。 与其中金属线直接接触FSG层的现有技术结构相比，氟贫化粘合层提供对金属线的增强的粘合性。 金属与底层电介质层的增强的粘附性对于在金属互连结构上使用无铅C4球的半导体封装提供更高的剥离性。

公开(公告)号：US08022543B2

公开(公告)日：2011-09-20

申请号：US12054713

申请日：2008-03-25

申请人： Mukta G. Farooq ,  Robert Hannon ,  Emily R. Kinser ,  Ian D. Melville

发明人： Mukta G. Farooq ,  Robert Hannon ,  Emily R. Kinser ,  Ian D. Melville

IPC分类号： H01L23/48

CPC分类号： H01L24/11 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/05552 ,  H01L2924/00014 ,  H01L2924/013

摘要： A first metallic diffusion barrier layer is formed on a last level metal plate exposed in an opening of a passivation layer. Optionally, a metallic adhesion promotion layer is formed on the first metallic diffusion barrier layer. An elemental metal conductive layer is formed on the metallic adhesion promotion layer, which provides a highly conductive structure that distributes current uniformly due to the higher electrical conductivity of the material than the layers above or below. A stack of the second metallic diffusion barrier layer and a wetting promotion layer is formed, on which a C4 ball is bonded. The elemental metal conductive layer distributes the current uniformly within the underbump metallurgy structure, which induces a more uniform current distribution in the C4 ball and enhanced electromigration resistance of the C4 ball.

摘要翻译： 第一金属扩散阻挡层形成在暴露在钝化层的开口中的最后一级金属板上。 任选地，在第一金属扩散阻挡层上形成金属粘附促进层。 在金属粘合促进层上形成元素金属导电层，其提供高导电性结构，其由于材料的导电性高于或高于上述层而导致电流均匀分布。 形成第二金属扩散阻挡层和润湿促进层的叠层，其上结合有C4球。 元素金属导电层将电流均匀分布在下焊管冶金结构内，从而在C4球中引起更均匀的电流分布，提高C4球的电迁移阻力。

公开(公告)号：US20110171827A1

公开(公告)日：2011-07-14

申请号：US12687282

申请日：2010-01-14

申请人： Mukta G. Farooq ,  Emily R. Kinser ,  Richard Wise ,  Hakeem Yusuff

发明人： Mukta G. Farooq ,  Emily R. Kinser ,  Richard Wise ,  Hakeem Yusuff

IPC分类号： H01L21/768

CPC分类号： H01L21/76847 ,  H01L21/0337 ,  H01L21/32136 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a substrate layer, etching the exposed planar area to form a cavity having a first depth in the structure, removing a second portion of the photoresist to expose a second planar area on the substrate layer, forming a doped portion in the second planar area, and etching the cavity to expose a first conductor in the structure and the doped portion to expose a second conductor in the structure.

摘要翻译： 一种方法包括在结构上图案化光致抗蚀剂层以限定开口并暴露衬底层上的第一平面区域，蚀刻暴露的平面区域以形成在结构中具有第一深度的空腔，将光致抗蚀剂的第二部分去除 在衬底层上露出第二平面区域，在第二平面区域中形成掺杂部分，并且蚀刻腔体以暴露结构中的第一导体和掺杂部分以暴露结构中的第二导体。

公开(公告)号：US20110095435A1

公开(公告)日：2011-04-28

申请号：US12607098

申请日：2009-10-28

申请人： Richard P. Volant ,  Mukta G. Farooq ,  Paul F. Findeis ,  Kevin S. Petrarca

发明人： Richard P. Volant ,  Mukta G. Farooq ,  Paul F. Findeis ,  Kevin S. Petrarca

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A through-silicon via (TSV) structure forming a unique coaxial or triaxial interconnect within the silicon substrate. The TSV structure is provided with two or more independent electrical conductors insulated from another and from the substrate. The electrical conductors can be connected to different voltages or ground, making it possible to operate the TSV structure as a coaxial or triaxial device. Multiple layers using various insulator materials can be used as insulator, wherein the layers are selected based on dielectric properties, fill properties, interfacial adhesion, CTE match, and the like. The TSV structure overcomes defects in the outer insulation layer that may lead to leakage. A method of fabricating such a TSV structure is also described.

摘要翻译： 硅通孔（TSV）结构在硅衬底内形成独特的同轴或三轴互连。 TSV结构设置有两个或更多个与另一个绝缘的独立电导体和与衬底绝缘的独立电导体。 电导体可以连接到不同的电压或接地，使得可以将TSV结构作为同轴或三轴装置进行操作。 使用各种绝缘材料的多层可用作绝缘体，其中根据介电性能，填充性能，界面粘合性，CTE匹配等来选择层。 TSV结构克服了外绝缘层中可能导致泄漏的缺陷。 还描述了制造这种TSV结构的方法。

公开(公告)号：US07919356B2

公开(公告)日：2011-04-05

申请号：US11831026

申请日：2007-07-31

申请人： Mukta G. Farooq ,  Robert Hannon ,  Dae-Young Jung ,  Ian D. Melville

发明人： Mukta G. Farooq ,  Robert Hannon ,  Dae-Young Jung ,  Ian D. Melville

IPC分类号： H01L21/44

CPC分类号： H01L21/563 ,  H01L24/32 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/26145 ,  H01L2224/29036 ,  H01L2224/321 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/831 ,  H01L2224/83379 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2224/05599

摘要： A method of assembling a microelectronic flip-chip arrangement includes attaching a chip having a defined length to a supporting substrate, wherein the chip forms a chip shadow line of the defined length on the supporting substrate, creating a first non-wettable zone on an outer portion of the bottom surface of the chip, creating a second non-wettable zone on a portion of the supporting substrate outside the chip shadow line, underfilling the chip and forming a fillet, wherein the fillet does not extend beyond the chip shadow line, and hardening the underfill including the fillet.

摘要翻译： 组装微电子倒装芯片布置的方法包括将具有限定长度的芯片附接到支撑衬底，其中芯片在支撑衬底上形成具有限定长度的芯片阴影线，在外部形成第一非可湿润区域 在芯片阴影线外部的支撑基板的一部分上形成第二不可润湿区域，在芯片上填充并形成圆角，其中圆角不延伸超过芯片阴影线，以及 硬化底部填充物，包括圆角。

公开(公告)号：US07816248B2

公开(公告)日：2010-10-19

申请号：US12138482

申请日：2008-06-13

申请人： Mukta G. Farooq ,  Lacrtis Economikos ,  Ian D. Melville ,  Kevin S. Petrarca ,  Richard P. Volant

发明人： Mukta G. Farooq ,  Lacrtis Economikos ,  Ian D. Melville ,  Kevin S. Petrarca ,  Richard P. Volant

IPC分类号： H01L21/44

CPC分类号： H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05085 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： Disclosed are embodiments of a far back end of the line solder connector and a method of forming the connector that eliminates the use aluminum, protects the integrity of the ball limiting metallurgy (BLM) layers and promotes adhesion of the BLM layers by incorporating a thin conformal conductive liner into the solder connector structure. This conductive liner coats the top of the via filling in any divots in order to create a uniform surface for BLM deposition and to, thereby, protect the integrity of the BLM layers. The liner further coats the dielectric sidewalls of the well in which the BLM layers are formed in order to enhance adhesion of the BLM layers to the well.

摘要翻译： 公开了线焊料连接器的远端的实施例以及形成连接器的方法，其消除了使用铝，保护了球限制冶金（BLM）层的完整性，并且通过并入薄的保形膜来促进BLM层的粘附 导电衬里进入焊接接头结构。 该导电衬里以通孔填充物的顶部涂覆任何刻痕，以便产生用于BLM沉积的均匀表面，从而保护BLM层的完整性。 衬垫还涂覆在其中形成BLM层的阱的电介质侧壁，以便增强BLM层与阱的粘合性。