利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

70 条记录 (耗时 0.047 秒)

    Semiconductor integrated circuit and electronic device
    31.
    发明授权
    Semiconductor integrated circuit and electronic device 有权
    半导体集成电路和电子设备

    公开(公告)号：US07725778B2

    公开(公告)日：2010-05-25

    申请号：US12314291

    申请日：2008-12-08

    申请人： Seiji Funaba ,  Yoji Nishio

    发明人： Seiji Funaba ,  Yoji Nishio

    IPC分类号： G11B20/20 ,  G11C29/00 ,  G01R31/26

    CPC分类号： G11C7/22 ,  G11C5/04 ,  G11C7/1045 ,  G11C7/222 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012 ,  H05K1/0248 ,  H05K1/0268 ,  H05K1/14 ,  H05K2201/044 ,  H05K2201/09781

    摘要： A dummy wiring 25 is provided for simulating an actual wiring 26 connecting semiconductor integrated circuits 2 and 6 on a circuit board. The semiconductor integrated circuit comprises a data output circuit 28 capable of variably setting the slew rate and a circuit 29 for measuring signal delay time between a signal sending point and a signal reflection point (characteristic impedance mismatching point) using the dummy wiring 25, and the delay time so obtained by the measuring circuit is used for the determination of the signal transition time of the output circuit. The transition time of the signal is set at least twice of the signal delay time between the signal sending point and the wiring branch at the nearest end. In this way, signal transmission with alleviated reflection by the reflection point at the nearest end is realized.

    摘要翻译： 虚拟布线25用于模拟连接电路板上的半导体集成电路2和6的实际布线26。 半导体集成电路包括能够可变地设置转换速率的数据输出电路28和用于使用虚拟布线25测量信号发送点和信号反射点之间的信号延迟时间的电路29（特征阻抗失配点），并且 由测量电路获得的延迟时间用于确定输出电路的信号转换时间。 信号的转换时间设置为信号发送点和最近端的布线支路之间的信号延迟时间的至少两倍。 以这种方式，实现了由最近端的反射点减轻反射的信号传输。

    Semiconductor device and timing control circuit
    35.
    再颁专利
    Semiconductor device and timing control circuit 有权
    半导体器件和定时控制电路

    公开(公告)号：USRE40205E1

    公开(公告)日：2008-04-01

    申请号：US10226019

    申请日：2002-08-23

    申请人： Seiji Funaba ,  Yoji Nishio ,  Yuichi Okuda ,  Yoshinobu Nakagome

    发明人： Seiji Funaba ,  Yoji Nishio ,  Yuichi Okuda ,  Yoshinobu Nakagome

    IPC分类号： G11C11/4076

    CPC分类号： G11C7/222 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/4076

    摘要： Control on the speed of operation of a delay loop from the output of a variable delay circuit to a delay control input thereof is performed. For example, frequency-dividing circuits are respectively placed at the input and output of the variable delay circuit. A signal obtained by frequency-dividing a signal outputted from the variable delay circuit is supplied to one input of a phase comparator through a dummy delay circuit, and a signal obtained by frequency-dividing the input of the variable delay circuit is supplied to the other input of the phase comparator. Phase control is performed according to the result of comparison between the phases of both signals. Control on the speed of operation of a delay loop from the output of a variable delay circuit to a delay control input thereof is performed. For example, frequency-dividing circuits are respectively placed at the input and output of the variable delay circuit. A signal obtained by frequency-dividing a signal outputted from the variable delay circuit is supplied to one input of a phase comparator through a dummy delay circuit, and a signal obtained by frequency-dividing the input of the variable delay circuit is supplied to the other input of the phase comparator. Phase control is performed according to the result of comparison between the phases of both signals.

    摘要翻译： <？delete-start id =“DEL-S-00001”date =“20080401”？从可变延迟电路的输出到延迟控制输入的延迟环路的操作速度进行控制。 例如，分频电路分别置于可变延迟电路的输入和输出端。 通过对从可变延迟电路输出的信号进行分频而获得的信号通过虚拟延迟电路被提供给相位比较器的一个输入，并且通过对可变延迟电路的输入进行分频而获得的信号被提供给另一个 输入相位比较器。 根据两个信号的相位比较结果执行相位控制。<？delete-end id =“DEL-S-00001”？> <？insert-start id =“INS-S-00001”date = 执行从可变延迟电路的输出到其延迟控制输入的延迟环的操作速度的控制。 例如，分频电路分别置于可变延迟电路的输入和输出端。 通过对从可变延迟电路输出的信号进行分频而获得的信号通过虚拟延迟电路被提供给相位比较器的一个输入，并且通过对可变延迟电路的输入进行分频而获得的信号被提供给另一个 输入相位比较器。 根据两个信号的相位之间的比较结果执行相位控制。<？insert-end id =“INS-S-00001”？>

    SEMICONDUCTOR DEVICE
    36.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20080054379A1

    公开(公告)日：2008-03-06

    申请号：US11675476

    申请日：2007-02-15

    申请人： Yoji Nishio ,  Yutaka Uematsu ,  Hideki Osaka ,  Tsutomu Hara ,  Seiji Funaba

    发明人： Yoji Nishio ,  Yutaka Uematsu ,  Hideki Osaka ,  Tsutomu Hara ,  Seiji Funaba

    IPC分类号： H01L29/94

    CPC分类号： G11C7/1078 ,  G11C7/1084 ,  G11C7/109

    摘要： Input circuit ensuring a noise margin for a reference voltage. A semiconductor chip 11a comprises a pad 14 that inputs a reference voltage Vref, an input circuit 13, a resistance element R1 connected between an input terminal of the input circuit 13 and the pad 14, a capacitance element C1 connected between the input terminal of the input circuit 13 and a power supply VDD, and a capacitance element C2 connected between the input terminal of the input circuit 13 and a ground VSS within the semiconductor chip. A resistance value of the resistance element R1 is set based on an impedance characteristic of a network, for supplying the reference voltage Vref.

    摘要翻译： 输入电路确保参考电压的噪声容限。 半导体芯片11a包括输入参考电压Vref的焊盘14，连接在输入电路13的输入端子和焊盘14之间的电阻元件R 1，连接在输入端13之间的电容元件C 1 输入电路13的端子和电源VDD，以及连接在输入电路13的输入端子和半导体芯片内的接地VSS之间的电容元件C 2。 基于网络的阻抗特性来设定电阻元件R 1的电阻值，用于提供基准电压Vref。

    Semiconductor integrated circuit and electronic device
    37.
    发明申请
    Semiconductor integrated circuit and electronic device 失效
    半导体集成电路和电子设备

    公开(公告)号：US20070255983A1

    公开(公告)日：2007-11-01

    申请号：US11270608

    申请日：2005-11-10

    申请人： Seiji Funaba ,  Yoji Nishio

    发明人： Seiji Funaba ,  Yoji Nishio

    IPC分类号： G01R31/28

    CPC分类号： G11C7/22 ,  G11C5/04 ,  G11C7/1045 ,  G11C7/222 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012 ,  H05K1/0248 ,  H05K1/0268 ,  H05K1/14 ,  H05K2201/044 ,  H05K2201/09781

    摘要： A dummy wiring 25 is provided for simulating an actual wiring 26 connecting semiconductor integrated circuits 2 and 6 on a circuit board. The semiconductor integrated circuit comprises a data output circuit 28 capable of variably setting the slew rate and a circuit 29 for measuring signal delay time between a signal sending point and a signal reflection point (characteristic impedance mismatching point) using the dummy wiring 25, and the delay time so obtained by the measuring circuit is used for the determination of the signal transition time of the output circuit. The transition time of the signal is set at least twice of the signal delay time between the signal sending point and the wiring branch at the nearest end. In this way, signal transmission with alleviated reflection by the reflection point at the nearest end is realized.

    摘要翻译： 虚拟布线25用于模拟连接电路板上的半导体集成电路2和6的实际布线26。 半导体集成电路包括能够可变地设置转换速率的数据输出电路28和用于使用虚拟布线25测量信号发送点和信号反射点之间的信号延迟时间的电路29（特征阻抗失配点），并且 通过测量电路获得的延迟时间用于确定输出电路的信号转换时间。 信号的转换时间设置为信号发送点和最近端的布线支路之间的信号延迟时间的至少两倍。 以这种方式，实现了由最近端的反射点减轻反射的信号传输。

    Memory system, module and register
    40.
    发明授权
    Memory system, module and register 有权
    内存系统，模块和寄存器

    公开(公告)号：US07051225B2

    公开(公告)日：2006-05-23

    申请号：US10427090

    申请日：2003-04-30

    申请人： Yoji Nishio ,  Kayoko Shibata ,  Seiji Funaba

    发明人： Yoji Nishio ,  Kayoko Shibata ,  Seiji Funaba

    IPC分类号： G06F1/04

    CPC分类号： G11C7/109 ,  G11C7/1078 ,  G11C7/1093

    摘要： Disclosed are a memory command address system and a memory module that can be operated not only for 266 MHzCLK but also for 200 MHzCLK, in which clock timings in the input sections of a PLL, a register, and a DRAM are matched to one another, a DLL (delay locked loop) is provided in the register, the output timing of CA signal from the register is controlled so that the setup time margin and the hold time margin of the CA signal with respect to the clock signal with the additional latency in the DRAM=1.5 or 2.0 are equated to each other, such that clock operation of 266 MHz, for example, is made possible. If both 266 MHz and 200 MHz are used, by taking account of the timing budget, control is made for retarding the timing of the CA signal input to the flip-flop which receives an internal clock signal (intCLK) supplied to the flip-flop for determining the CA signal output timing from the register. Alternatively, control is made for switching between the replica (replical) provided in the register and an output unit associated with the replica, depending on the frequency being used, so as to cope with both frequencies simply by providing one sort of the module and one sort of the register.

    摘要翻译： 公开了一种存储器命令地址系统和存储器模块，其不仅可以用于266MHzCLK，而且可以用于200MHzCLK，其中PLL，寄存器和DRAM的输入部分中的时钟定时彼此匹配， 在寄存器中提供DLL（延迟锁定环），控制来自寄存器的CA信号的输出定时，使得CA信号的建立时间余量和保持时间裕度相对于时钟信号具有额外的等待时间 DRAM = 1.5或2.0彼此相等，使得例如266MHz的时钟操作成为可能。 如果使用266MHz和200MHz，通过考虑时序预算，进行控制以延迟输入到触发器的CA信号的定时，该触发器接收提供给触发器的内部时钟信号（intCLK） 用于确定来自寄存器的CA信号输出定时。 或者，根据所使用的频率，进行控制以在寄存器中提供的副本（复制）和与副本相关联的输出单元之间进行切换，从而简单地通过提供一种模块和一个模块来处理两个频率 排序的注册表。