公开(公告)号：US06762506B2

公开(公告)日：2004-07-13

申请号：US10337930

申请日：2003-01-07

申请人： Masazumi Amagai ,  Masako Watanabe

发明人： Masazumi Amagai ,  Masako Watanabe

IPC分类号： H01L2348

CPC分类号： H05K3/3463 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/244 ,  H05K3/3436 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： Apparatus and method for assembling a semiconductor device on a wiring substrate is disclosed, wherein Pb (lead) is not used and the chance of generation of defects is reduced. Semiconductor package (100) has solder balls (114) containing Sn (tin), Ag (silver) and Cu (copper). Wiring substrate 200 has connecting terminals 208 for connecting solder balls (114). The connecting terminals (208) have an Au (gold) layer (212) and a Ni layer (210). In the operation for assembling semiconductor package (100) onto wiring substrate (200), because solder balls (114) are heated and fixed on connecting terminals (208), Au in Au layer (212) diffuses into balls (114). Because Au is contained in solder balls (114), a high bonding strength is obtained, and the chance of generation of defects is reduced.

摘要翻译： 公开了一种用于在布线基板上组装半导体器件的装置和方法，其中不使用Pb（铅），并且减少了产生缺陷的机会。 半导体封装（100）具有包含Sn（锡），Ag（银）和Cu（铜）的焊球（114）。 接线基板200具有用于连接焊球（114）的连接端子208。 连接端子（208）具有Au（金）层（212）和Ni层（210）。 在将半导体封装（100）组装到布线基板（200）上的操作中，由于焊球（114）被加热固定在连接端子（208）上，Au层（212）中的Au扩散到球（114）中。 由于Au包含在焊球（114）中，因此获得高的接合强度，并且产生缺陷的机会降低。

公开(公告)号：US08193085B2

公开(公告)日：2012-06-05

申请号：US12703267

申请日：2010-02-10

申请人： Masako Watanabe ,  Masazumi Amagai

发明人： Masako Watanabe ,  Masazumi Amagai

IPC分类号： H01L21/44

CPC分类号： H05K3/3478 ,  H01L21/563 ,  H01L24/29 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11334 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81101 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83101 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/351 ,  H05K3/3436 ,  H05K2201/0129 ,  H05K2201/10424 ,  H05K2201/10977 ,  H05K2203/041 ,  Y02P70/613 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor device (1700), which comprises a workpiece (1201) with an outline (1711) and a plurality of contact pads (1205) and further an external part (1701) with a plurality of terminal pads (1702). This part is spaced from the workpiece, and the terminal pads are aligned with the workpiece contact pads, respectively. A reflow element (1203) interconnects each of the contact pads with its respective terminal pad. Thermoplastic material (1204) fills the space between the workpiece and the part; this material adheres to the workpiece, the part and the reflow elements. Further, the material has an outline (1711) substantially in line with the outline of the workpiece, and fills the space (1707) substantially without voids. Due to the thermoplastic character of the filling material, the finished device can be reworked, when the temperature range for reflowing the reflow elements is reached.

摘要翻译： 一种半导体器件（1700），其包括具有轮廓（1711）的工件（1201）和多个接触焊盘（1205）以及具有多个端子焊盘（1702）的外部部分（1701）。 该部件与工件间隔开，端子焊盘分别对准工件接触焊盘。 回流元件（1203）将每个接触焊盘与其相应的端子焊盘互连。 热塑性材料（1204）填充工件与零件之间的空间; 该材料粘附到工件，部件和回流元件上。 此外，材料具有基本上与工件的轮廓一致的轮廓（1711），并且基本上没有空隙填充空间（1707）。 由于填充材料的热塑性特征，当达到回流元件的温度范围时，可以对成品装置进行再加工。

公开(公告)号：US08097964B2

公开(公告)日：2012-01-17

申请号：US12648871

申请日：2009-12-29

申请人： Jeffrey Alan West ,  Margaret Rose Simmons-Matthews ,  Masazumi Amagai

发明人： Jeffrey Alan West ,  Margaret Rose Simmons-Matthews ,  Masazumi Amagai

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit (IC) includes a substrate having a top side having active circuitry thereon including a plurality of metal interconnect levels including a first metal interconnect level and a top metal interconnect level, and a bottom side. At least one TSV array includes a plurality of TSVs. The TSVs are positioned in rows including a plurality of interior rows and a pair of exterior rows and a plurality of columns including a plurality of interior columns and a pair of exterior columns. At least a portion of the TSVs in the array are electrically connected TSVs that are coupled to a TSV terminating metal interconnect level selected from the plurality of metal interconnect levels. At least one of the exterior rows or exterior columns include a lower number of electrically connected TSVs compared to a maximum number of electrically connected TSVs in the interior rows and interior columns, respectively.

摘要翻译： 集成电路（IC）包括其上具有有源电路的顶面的衬底，其上包括多个金属互连级，包括第一金属互连级和顶金属互连级，以及底侧。 至少一个TSV阵列包括多个TSV。 TSV定位成包括多个内部行和一对外部行以及包括多个内部列和一对外部列的多个列的行。 阵列中的TSV的至少一部分是电连接的TSV，其被耦合到从多个金属互连级别中选择的TSV端接金属互连级别。 与内部行和内部列中的最多数量的电连接的TSV相比，外部列或外部列中的至少一个包括较少数量的电连接的TSV。

公开(公告)号：US20100090323A1

公开(公告)日：2010-04-15

申请号：US12446813

申请日：2007-10-22

申请人： Tomonori Shinoda ,  Hironori Shizuhata ,  Hirofumi Shinoda ,  Yuji Kawamata ,  Takeshi Tashima ,  Masato Shimamura ,  Masako Watanabe ,  Masazumi Amagai

发明人： Tomonori Shinoda ,  Hironori Shizuhata ,  Hirofumi Shinoda ,  Yuji Kawamata ,  Takeshi Tashima ,  Masato Shimamura ,  Masako Watanabe ,  Masazumi Amagai

IPC分类号： H01L23/52 ,  H05K7/00 ,  H01L21/60

CPC分类号： H01L25/105 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

摘要： The present invention provides a spacer sheet for a complex type semiconductor device provided between the semiconductor packages of a complex type semiconductor device formed by laminating plural semiconductor packages, comprising through holes of an array corresponding to electrodes which can be provided onto a substrate of one semiconductor package and which are formed in order to connect and wire one semiconductor package with the other semiconductor package and a space part corresponding to a principal part of the above one semiconductor package mounted on the substrate or a principal part of the other semiconductor package opposed to the substrate and a production process for a complex type semiconductor device in which the above spacer sheet is used. It further provides a wiring and connecting method by using a spacer sheet which satisfies securing of a distance between connection terminals and a narrow pitch at the same time in a POP type semiconductor package and a complex type semiconductor device of a POP type which is increased in a packaging density by the above wiring and connecting method.

摘要翻译： 本发明提供了一种复合型半导体器件的间隔片，其设置在通过层叠多个半导体封装形成的复合型半导体器件的半导体封装之间，该半导体封装包括与可设置在一个半导体的衬底上的电极相对应的阵列的通孔 封装，并且其形成以便将一个半导体封装与另一个半导体封装连接并布线，并且与安装在基板上的上述一个半导体封装的主要部分相对应的空间部分或与其相对的另一个半导体封装的主要部分 基板和其中使用上述间隔片的复合型半导体器件的制造方法。 它还通过使用在POP型半导体封装中同时满足连接端子之间的距离和窄间距的间隔片以及POP型的复合型半导体器件进一步提供布线和连接方法，所述复合型半导体器件增加 通过上述布线和连接方法的封装密度。

公开(公告)号：US07626274B2

公开(公告)日：2009-12-01

申请号：US11346728

申请日：2006-02-03

申请人： Masazumi Amagai

发明人： Masazumi Amagai

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L23/40

CPC分类号： H01L23/3128 ,  B23K35/262 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13021 ,  H01L2224/13111 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/81447 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/351 ,  H05K3/244 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/10992 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/01047 ,  H01L2924/01028 ,  H01L2924/01027

摘要： A semiconductor device with an improved solder joint system is described. The solder system includes two copper contact pads connected by a body of solder and the solder is an alloy including tin, silver, and at least one metal from the transition groups IIIA, IVA, VA, VIA, VIIA, and VIIIA of the Periodic Table of the Elements. The solder joint system also includes, between the pads and the solder, layers of intermetallic compounds, which include grains of copper and tin compounds and copper, silver, and tin compounds. The compounds contain the transition metals. The inclusion of the transition metals in the compound grains reduce the compound grains size and prevent grain size increases after the solder joint undergoes repeated solid/liquid/solid cycles.

摘要翻译： 描述了具有改进的焊点系统的半导体器件。 焊料系统包括通过焊料体连接的两个铜接触焊盘，焊料是包含锡，银以及来自周期表的过渡族IIIA，IVA，VA，VIA，VIIA和VIIIA中的至少一种金属的合金 的元素。 焊点系统还在焊盘和焊料之间包括金属间化合物层，其包括铜和锡化合物的晶粒以及铜，银和锡化合物。 化合物含有过渡金属。 过渡金属在复合晶粒中的包含减少了复合晶粒尺寸，并防止了焊点经历重复的固/液/固体循环之后的晶粒尺寸增加。

公开(公告)号：US20080048303A1

公开(公告)日：2008-02-28

申请号：US11466219

申请日：2006-08-22

申请人： Masazumi Amagai ,  Kenji Masumoto

发明人： Masazumi Amagai ,  Kenji Masumoto

IPC分类号： H01L23/495

CPC分类号： H01L23/3128 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/48 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In one aspect, the invention provides a semiconductor device that comprises a semiconductor device packaging substrate core. A first interconnect structure is located within a mold region and on a die side of the substrate core and has a first conductive metal density associated therewith. A second interconnect structure is located within the mold region and on a solder joint side of the substrate core and has a second conductive metal density associated therewith, wherein the second conductive metal density within the mold region is about equal to or less than the first conductive metal density within the mold region.

摘要翻译： 一方面，本发明提供一种包括半导体器件封装衬底芯的半导体器件。 第一互连结构位于模具区域内并且在衬底芯的裸片侧上并且具有与其相关联的第一导电金属密度。 第二互连结构位于模具区域内并且位于衬底芯的焊接侧上并且具有与其相关联的第二导电金属密度，其中模具区域内的第二导电金属密度约等于或小于第一导电 模具区域内的金属密度。

公开(公告)号：US07282175B2

公开(公告)日：2007-10-16

申请号：US10824647

申请日：2004-04-15

申请人： Masazumi Amagai ,  Masako Watanabe ,  Kensho Murata ,  Yoshitaka Toyoda ,  Minoru Ueshima ,  Tsukasa Ohnishi ,  Takeshi Tashima ,  Daisuke Souma ,  Takahiro Roppongi ,  Hiroshi Okada

发明人： Masazumi Amagai ,  Masako Watanabe ,  Kensho Murata ,  Yoshitaka Toyoda ,  Minoru Ueshima ,  Tsukasa Ohnishi ,  Takeshi Tashima ,  Daisuke Souma ,  Takahiro Roppongi ,  Hiroshi Okada

IPC分类号： C22C13/02

CPC分类号： B23K35/262 ,  B23K2101/36

摘要： A lead-free solder includes 0.05-5 mass % of Ag, 0.01-0.5 mass % of Cu, at least one of P, Ge, Ga, Al, and Si in a total amount of 0.001-0.05 mass %, and a remainder of Sn. One or more of a transition element for improving resistance to heat cycles, a melting point lowering element such as Bi, In, or Zn, and an element for improving impact resistance such as Sb may be added.

摘要翻译： 无铅焊料包括0.05-5质量％的Ag，0.01-0.5质量％的Cu，至少一种P，Ge，Ga，Al和Si，总量为0.001-0.05质量％，余量为 的Sn。 可以添加用于提高耐热循环性的过渡元素中的一种或多种，​​诸如Bi，In或Zn的熔点降低元素，以及用于改善抗冲击性的元素如Sb。

公开(公告)号：US20050036902A1

公开(公告)日：2005-02-17

申请号：US10614351

申请日：2003-07-08

申请人： Masazumi Amagai ,  Masako Watanabe ,  Osamu Munekata ,  Yoshitaka Toyoda ,  Minoru Ueshima ,  Tsukasa Ohnishi ,  Hiroshi Okada

发明人： Masazumi Amagai ,  Masako Watanabe ,  Osamu Munekata ,  Yoshitaka Toyoda ,  Minoru Ueshima ,  Tsukasa Ohnishi ,  Hiroshi Okada

IPC分类号： B23K35/02 ,  B23K35/26 ,  C22C13/00

CPC分类号： B23K35/262 ,  B23K35/0244 ,  B23K2101/42

摘要： A lead-free solder alloy comprises 1.0-5.0 wt % Ag, 0.01-0.5 wt % Ni, one or both of (a) 0.001-0.05 wt % Co and (b) at least one of P, Ge, and Ga in a total amount of 0.001-0.05 wt %, and a remainder of Sn. The solder can form solder bumps which have a high bonding strength and which do not undergo yellowing after soldering.

摘要翻译： 一种无铅焊料合金包含1.0-5.0重量％的Ag，0.01-0.5重量％的Ni，（a）0.001-0.05重量％的Co中的一个或两个，和（b）一个或多个P，Ge和Ga中的至少一个， 总量为0.001-0.05重量％，余量为Sn。 焊料可以形成具有高粘合强度并且在焊接后不经历黄变的焊料凸块。

公开(公告)号：US06602803B2

公开(公告)日：2003-08-05

申请号：US09401572

申请日：1999-09-22

申请人： Chee Kiang Yew ,  Masazumi Amagai

发明人： Chee Kiang Yew ,  Masazumi Amagai

IPC分类号： H01L2131

CPC分类号： H01L23/3142 ,  H01L23/24 ,  H01L23/3114 ,  H01L23/3128 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/16245 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/49 ,  H01L2224/73215 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method for attaching an integrated circuit chip to an organic substrate comprising the steps of providing an integrated circuit chip having an active and a passive surface, said active surface including a protective polymer layer; activating said polymer layer by exposing it to reactive ion etching plasma, thereby increasing the surface roughness and imparting affinity to adhesion; providing an electrically insulating substrate having first and second surfaces; and contacting said second surface of said substrate to said activated polymer layer on said chip, whereby strong adhesion is exerted at the interface between said layer and said substrate, directly attaching said substrate to said chip.

摘要翻译： 一种用于将集成电路芯片附着到有机基板的方法，包括以下步骤：提供具有有源和无源表面的集成电路芯片，所述活性表面包括保护性聚合物层; 通过将其暴露于反应离子蚀刻等离子体来活化所述聚合物层，从而增加表面粗糙度并赋予粘合亲和力; 提供具有第一和第二表面的电绝缘基板; 并使所述基板的所述第二表面与所述芯片上的所述活化聚合物层接触，从而在所述层与所述基板之间的界面处施加强烈的粘附力，将所述基板直接连接到所述芯片上。

公开(公告)号：US06232661B1

公开(公告)日：2001-05-15

申请号：US09352109

申请日：1999-07-14

申请人： Masazumi Amagai ,  Norihito Umehara ,  Kiyoshi Yajima

发明人： Masazumi Amagai ,  Norihito Umehara ,  Kiyoshi Yajima

IPC分类号： H01L2348

CPC分类号： H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/32013 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/8547 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： The purpose is to improve the assembly reliability of the BGA package. The present invention provides a type of BGA semiconductor device having plural conductor bumps arranged two-dimensionally on one surface of the insulating substrate. In this semiconductor device, there is adhesive layer (8) for attaching semiconductor chip (2) to said insulating substrate (3). According to the present invention, the outer edge of said adhesive layer (8) extends beyond the outer edge of said semiconductor chip (2). When the semiconductor device of the present invention is assembled on the external substrate, the stress forces that are caused by the difference in the linear expansion coefficient between semiconductor chip (2) and the external substrate and which propagate from the outer edge of the semiconductor chip to the joint of the conductor bumps located directly below the outer edge can be reduced by an adhesive layer (8) that extends beyond the outer side edge of said semiconductor chip (2), and the shear forces are reduced in the joint.

摘要翻译： 目的是提高BGA封装的组装可靠性。 本发明提供了一种在绝缘基板的一个表面上具有二维布置的多个导体凸块的BGA半导体器件。 在该半导体器件中，存在用于将半导体芯片（2）附着到所述绝缘基板（3）的粘合层（8）。 根据本发明，所述粘合剂层（8）的外边缘延伸超过所述半导体芯片（2）的外边缘。 当本发明的半导体器件组装在外部基板上时，由半导体芯片（2）和外部基板之间的线膨胀系数的差异引起的并且从半导体芯片的外边缘传播的应力 可以通过延伸超过所述半导体芯片（2）的外侧边缘的粘合剂层（8）来减少位于外边缘正下方的导体凸块的接头，并且在接头中剪切力减小。