公开(公告)号：US20010034076A1

公开(公告)日：2001-10-25

申请号：US09771872

申请日：2001-01-29

Applicant: Analog Devices, Inc.

Inventor： John R. Martin

IPC: H01L021/00

CPC classification number: H01L21/3122 ,  B81B3/0005 ,  B81C1/0096 ,  B81C2201/0176 ,  B81C2201/112 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02263 ,  H01L24/05 ,  H01L24/45 ,  H01L2224/05624 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48624 ,  H01L2224/73265 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/16152 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014

Abstract: This invention discloses a process for forming durable anti-stiction surfaces on micromachined structures while they are still in wafer form (i.e., before they are separated into discrete devices for assembly into packages). This process involves the vapor deposition of a material to create a low stiction surface. It also discloses chemicals which are effective in imparting an anti-stiction property to the chip. These include polyphenylsiloxanes, silanol terminated phenylsiloxanes and similar materials.

Abstract translation: 本发明公开了一种在微加工结构上形成持久的抗静电表面的方法，同时它们仍然是晶片形式（即，在它们被分离成用于组装成包装的分立装置之前）。 该方法涉及材料的气相沉积以产生低粘度表面。 它还公开了有效赋予芯片抗静电性能的化学品。 这些包括聚苯基硅氧烷，硅烷醇封端的苯基硅氧烷和类似的材料。

公开(公告)号：US20240067520A1

公开(公告)日：2024-02-29

申请号：US18239986

申请日：2023-08-30

Applicant: Infineon Technologies AG

Inventor： Fabian Streb ,  Johann Straßer ,  Hans-Jörg Timme ,  Marc Füldner ,  Arnaud Walther ,  Hutomo Suryo Wasisto

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81C1/00952 ,  B81B3/0005 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81B2203/04 ,  B81C2201/0114 ,  B81C2201/0133 ,  B81C2201/0176 ,  B81C2201/112

Abstract: An encapsulated MEMS device and a method for manufacturing the MEMS device are provided. The method comprises providing a cavity structure having an inner volume comprising a plurality of MEMS elements, which are relatively displaceable with respect to each other, and having an opening structure to the inner volume, depositing a Self-Assembled Monolayer (SAM) through the opening structure onto exposed surfaces within the inner volume of the cavity structure, and closing the cavity structure by applying a layer structure on the opening structure for providing a hermetically closed cavity.

公开(公告)号：US11883845B2

公开(公告)日：2024-01-30

申请号：US18093701

申请日：2023-01-05

Applicant: BFLY OPERATIONS, INC.

Inventor： Lingyun Miao ,  Keith G. Fife ,  Jianwei Liu ,  Jonathan M. Rothberg

IPC: B06B1/02 ,  B81B3/00 ,  B81C1/00

CPC classification number: B06B1/0292 ,  B81B3/001 ,  B81C1/00984 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81B2203/0392 ,  B81C2201/0109 ,  B81C2201/0125 ,  B81C2201/0176

Abstract: A method of forming an ultrasonic transducer device involves depositing a first layer on a substrate, depositing a second layer on the first layer, patterning the second layer at a region corresponding to a location of a transducer cavity, depositing a third layer that refills regions created by patterning the second layer, planarizing the third layer to a top surface of the second layer, removing the second layer, conformally depositing a fourth layer over the first layer and the third layer, defining the transducer cavity in a support layer formed over the fourth layer; and bonding a membrane to the support layer.

公开(公告)号：US20230357000A1

公开(公告)日：2023-11-09

申请号：US17811109

申请日：2022-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Jung Chen

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81C1/00158 ,  B81B3/0021 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81B2203/0353 ,  B81B2203/04 ,  B81C2201/0125 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/014 ,  B81C2201/0176

Abstract: A membrane is formed through processes including depositing a first piezoelectrical layer, depositing a first electrode layer over the first piezoelectrical layer, patterning the first electrode layer to form a first electrode, depositing a second piezoelectrical layer over the first electrode, depositing a second electrode layer over the second piezoelectrical layer, patterning the second electrode layer to form a second electrode, and depositing a third piezoelectrical layer over the second electrode. The third piezoelectrical layer, the second piezoelectrical layer, and the first piezoelectrical layer are etched to form a through-hole. The through-hole is laterally spaced apart from the first electrode and the second electrode. A first contact plug and a second contact plug are then formed to electrically connect to the first electrode and the second electrode, respectively.

公开(公告)号：US11667524B2

公开(公告)日：2023-06-06

申请号：US17130335

申请日：2020-12-22

Applicant: HYUNDAI KEFICO CORPORATION

Inventor： Jun Hwan Choi ,  Chi Yeon Kim

IPC: B81C1/00 ,  G01L19/06

CPC classification number: B81C1/00357 ,  B81C2201/0133 ,  B81C2201/0176 ,  B81C2201/0178 ,  B81C2201/0195 ,  G01L19/0654

Abstract: Disclose is a method for fabricating a semiconductor device. The method includes: forming a groove such as by etching one side surface of a first substrate; attaching a second substrate including a silicon layer on the etched surface of the first substrate formed with the hollow groove; etching the second substrate so as to leave substantially only the silicon layer; forming a thin film structure on the surface of silicon layers of the second substrate; and separating the second substrate formed with the thin film structure from the first substrate. For example, the groove structure may be formed in the lower portion of the device in the process of fabricating the semiconductor device to facilitate the final device separation.

公开(公告)号：US11667517B2

公开(公告)日：2023-06-06

申请号：US16908243

申请日：2020-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chia Liu ,  Chia-Hua Chu ,  Chun-Wen Cheng

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/0006 ,  B81B7/0051 ,  B81C1/00246 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2201/0271 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/0176 ,  B81C2201/0181 ,  B81C2201/112 ,  B81C2203/0714 ,  B81C2203/0735

Abstract: Representative methods for sealing MEMS devices include depositing insulating material over a substrate, forming conductive vias in a first set of layers of the insulating material, and forming metal structures in a second set of layers of the insulating material. The first and second sets of layers are interleaved in alternation. A dummy insulating layer is provided as an upper-most layer of the first set of layers. Portions of the first and second set of layers are etched to form void regions in the insulating material. A conductive pad is formed on and in a top surface of the insulating material. The void regions are sealed with an encapsulating structure. At least a portion of the encapsulating structure is laterally adjacent the dummy insulating layer, and above a top surface of the conductive pad. An etch is performed to remove at least a portion of the dummy insulating layer.

公开(公告)号：US11644435B2

公开(公告)日：2023-05-09

申请号：US16845565

申请日：2020-04-10

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： ShuaiGang Xiao ,  David S. Kuo ,  Xiaomin Yang ,  Kim Yang Lee ,  Yautzong Hsu ,  Michael R. Feldbaum

IPC: G01R27/08 ,  G01N27/327 ,  G01N33/487 ,  C12Q1/6869 ,  C23C14/00 ,  B01L3/00 ,  G01N27/414 ,  G01N27/447 ,  B82Y5/00

CPC classification number: G01N27/3278 ,  B01L3/502707 ,  B01L3/502715 ,  B01L3/502761 ,  C12Q1/6869 ,  C23C14/00 ,  G01N27/4145 ,  G01N27/4146 ,  G01N27/44791 ,  G01N33/48721 ,  B81C2201/0143 ,  B81C2201/0176 ,  B81C2201/0181 ,  B82Y5/00

Abstract: A DNA sequencing device and methods of making. The device includes a pair of electrodes having a spacing of no greater than about 2 nm, the electrodes being exposed within a nanopore to measure a DNA strand passing through the nanopore. The device can be made by depositing a conductive layer over a sacrificial channel and then removing the sacrificial channel to form the electrode gap.

公开(公告)号：US20180299335A1

公开(公告)日：2018-10-18

申请号：US15753147

申请日：2016-07-08

Applicant: INSTITUTE OF CEOLOGY AND GEOPHYSICS, CHINESE ACADEMY OF SCIENCES

Inventor： Man WONG ,  Kevin CHAU

IPC: G01L1/18 ,  G01B7/16 ,  B81B7/02 ,  B81C1/00

CPC classification number: G01L1/18 ,  B81B7/02 ,  B81B2201/0292 ,  B81B2203/0109 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81C1/00547 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/0176 ,  G01B7/18 ,  G01B7/20 ,  G01L1/26

Abstract: The present invention is related to a sensor. In particular, the present invention is related to a MEMS strain gauge die and its fabrication process. The MEMS strain gauge die comprises a handle, a device layer and a cap all connected together. A silicon oxide layer is formed between the handle and the device layer. Another silicon oxide layer is formed between the device layer and the cap. Recesses are respectively formed on the handle and the cap and face each other. The handle recess and the cap recess are connected to form a cavity. The device layer, which spans the cavity, further comprises a bridge on which a plurality of piezoresistive sensing elements are formed. The present strain gauge die is more immune to temperature effects. It is especially suitable for operating in a high temperature environment and is capable of delivering accurate and reliable strain measurements at low cost.

公开(公告)号：US10081533B2

公开(公告)日：2018-09-25

申请号：US14448767

申请日：2014-07-31

Applicant: Infineon Technologies AG

Inventor： Ulrich Schmid ,  Tobias Frischmuth ,  Peter Irsigler ,  Thomas Grille ,  Daniel Maurer ,  Ursula Hedenig ,  Markus Kahn ,  Günter Denifl

IPC: B81B3/00 ,  B06B1/02 ,  B81C1/00 ,  H04R19/02 ,  H04R19/04 ,  H04R31/00 ,  H04R7/24 ,  H04R7/02 ,  H04R19/00

CPC classification number: B81B3/0021 ,  B06B1/02 ,  B81B3/007 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2203/0109 ,  B81B2203/0118 ,  B81B2203/0127 ,  B81B2203/051 ,  B81C1/00142 ,  B81C1/0015 ,  B81C1/00158 ,  B81C1/00373 ,  B81C2201/0176 ,  B81C2201/0181 ,  B81C2201/019 ,  H04R7/02 ,  H04R7/24 ,  H04R19/005 ,  H04R19/02 ,  H04R19/04 ,  H04R31/00 ,  H04R31/003 ,  H04R2201/003 ,  H04R2307/023 ,  H04R2400/01 ,  H04R2499/11

Abstract: A micromechanical structure includes a substrate and a functional structure arranged at the substrate. The functional structure has a functional region configured to deflect with respect to the substrate responsive to a force acting on the functional region. The functional structure includes a conductive base layer and a functional structure comprising a stiffening structure having a stiffening structure material arranged at the conductive base layer and only partially covering the conductive base layer at the functional region. The stiffening structure material includes a silicon material and at least a carbon material.

公开(公告)号：US20180186625A1

公开(公告)日：2018-07-05

申请号：US15395029

申请日：2016-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Simon Joshua JACOBS ,  Molly Nelis SING ,  Kelly Jay TAYLOR

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0075 ,  B81B2207/07 ,  B81C1/0038 ,  B81C2201/0132 ,  B81C2201/0176

Abstract: In described examples, a method of forming a microelectromechanical device comprises: forming a first metallic layer comprising a conducting layer on a substrate; forming a first dielectric layer on the first metallic layer, wherein the first dielectric layer comprises one or more individual dielectric layers; forming a sacrificial layer on the first dielectric layer; forming a second dielectric layer on the sacrificial layer; forming a second metallic layer on the second dielectric layer; and removing the sacrificial layer to form a spacing between the second dielectric layer and the first dielectric layer. Removing the sacrificial layer enables movement of the second dielectric layer relative to the first dielectric layer in at least one direction.