公开(公告)号：US20190221448A1

公开(公告)日：2019-07-18

申请号：US15870751

申请日：2018-01-12

申请人： AIS Technology, Inc.

发明人： Raymond W. Bae

IPC分类号： H01L21/48 ,  H01L49/02 ,  H01L21/66 ,  H01L23/58

CPC分类号： H01L21/4885 ,  H01L22/30 ,  H01L23/58 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L2225/06596

摘要： An embodiment of the present invention provides a method and system of manufacturing a redistribution platform comprising: providing a substrate; patterning a first layer of a routing trace over the substrate where the first layer of the routing trace includes a conductive material forming part of a circuit element; semi-curing a first translucent or transparent material around the first layer of the routing trace; testing the first layer of the routing trace; patterning a second layer of the routing trace over the first translucent or transparent material where the second layer of the routing trace includes a further conductive material which is the same as the conductive material forming part of the circuit element and attached to the conductive material of the first layer of the routing trace; and fully curing the first translucent or transparent material subsequent to the patterning of the second layer of the routing trace.

公开(公告)号：US09997435B2

公开(公告)日：2018-06-12

申请号：US15243255

申请日：2016-08-22

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： John P. Karidis ,  Mark D. Schultz

IPC分类号： B23K31/02 ,  H01L23/473 ,  H01L21/48 ,  H01L23/467 ,  B23K1/00 ,  B23K101/14

CPC分类号： H01L23/473 ,  B23K1/0014 ,  B23K31/02 ,  B23K2101/14 ,  H01L21/4882 ,  H01L21/4885 ,  H01L23/3677 ,  H01L23/467 ,  H01L24/72 ,  H01L2924/01322 ,  H01L2924/00

摘要： A heat sink includes a plurality of layers being disposed substantially parallel with a surface of a heat source. The layers include a plurality of pin portions spaced apart from each other in a planar arrangement wherein the pin portions of the layers are stacked and bonded to form pin fins extending in a transverse direction relative to the heat source to sink heat. A compliant layer is disposed between the pin fins and a mechanical load. The compliant layer provides compliance such that the pin fins accommodate dimensional differences when interfacing with the heat source.

公开(公告)号：US09640413B2

公开(公告)日：2017-05-02

申请号：US14901878

申请日：2013-12-02

申请人： Jiangsu Changjiang Electronics Technology Co., Ltd

发明人： Steve Xin Liang ,  Chih-Chung Liang ,  Yu-Bin Lin ,  Yaqin Wang ,  Youhai Zhang

IPC分类号： H01L21/00 ,  H01L21/48 ,  H01L23/495 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L21/4832 ,  H01L21/48 ,  H01L21/4825 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4871 ,  H01L21/4885 ,  H01L21/4889 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49517 ,  H01L23/49531 ,  H01L23/49548 ,  H01L23/49565 ,  H01L23/49575 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/49111 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/85399

摘要： Provided is an etching-before-packaging horizontal chip three-dimensional system level metal circuit board structure comprising a metal substrate frame; the metal substrate frame is provided with base islands and pins therein; the front faces of the base islands are provided with chips; the front faces of the chips are connected to the front faces of the pins via metal wires; conductive posts are disposed on the front faces or back faces of the pins; the peripheral areas of the base islands, the areas between the base islands and the pins, the areas between the pins, the areas above the base islands and the pins, the areas below the base islands and the pins, and the exteriors of the chips, the metal wires and the conductive posts are all encapsulated with molding compound.

公开(公告)号：US09514966B2

公开(公告)日：2016-12-06

申请号：US14251236

申请日：2014-04-11

申请人： QUALCOMM Incorporated

发明人： Siamak Fazelpour ,  Charles David Paynter ,  Ryan David Lane

IPC分类号： H01L23/58 ,  H01L21/48 ,  H01L23/552 ,  H01L23/66 ,  H01R13/6471

CPC分类号： H01L21/4885 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6638 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/1579 ,  H01R13/6471

摘要： The disclosure is related to pin layouts in a semiconductor package. One embodiment of the disclosure provides a rhombus shaped shared reference pin layout that isolates a set of differential pin pairs. The differential signal pin pairs are configured such that an axis formed by a vertical signal pin pair is orthogonal to and mutually bisecting an axis formed by a lateral signal pin pair.

摘要翻译： 本公开涉及半导体封装中的引脚布局。 本公开的一个实施例提供了一种隔离一组差分引脚对的菱形共享参考引脚布局。 差分信号引脚对被配置为使得由垂直信号引脚对形成的轴线与横向信号引脚对形成的轴线正交并相互平分。

公开(公告)号：US09470652B1

公开(公告)日：2016-10-18

申请号：US14854265

申请日：2015-09-15

申请人： FREESCALE SEMICONDUCTOR, INC.

发明人： Stephen R. Hooper ,  Leo M. Higgins, III ,  Raymond M. Roop

IPC分类号： H01L21/00 ,  G01N27/414

CPC分类号： G01N27/4148 ,  G01N27/4145 ,  H01L21/00 ,  H01L21/4885

摘要： A sensing device includes a sensor die having a sensing region formed at a first surface of the sensor die. The sensing device further includes an encapsulant covering the sensing die, the encapsulant having a cavity formed therein, wherein the cavity exposes the sensing region. A sensitive membrane material is deposited within the cavity over the sensing region. A method of manufacturing sensing devices entails mounting a plurality of sensing dies to a carrier, encapsulating the dies in an encapsulant, forming cavities in the encapsulant, the cavities exposing a sensing region of each sensor die, and depositing the sensitive membrane material within each of the cavities. The encapsulating and forming operations can be performed simultaneously using a film-assisted molding (FAM) process, and the depositing operation is performed following FAM at an ambient temperature that is lower than the temperature needed to perform FAM.

摘要翻译： 感测装置包括具有形成在传感器管芯的第一表面处的感测区域的传感器管芯。 感测装置还包括覆盖感测裸片的密封剂，所述密封剂具有形成在其中的空腔，其中所述空腔暴露感测区域。 敏感膜材料沉积在感应区域内的空腔内。 制造感测装置的方法需要将多个感测管芯安装到载体上，将管芯封装在密封剂中，在密封剂中形成空腔，使空腔暴露每个传感器管芯的感测区域，并将敏感膜材料沉积在每个 空腔。 封装和成型操作可以使用薄膜辅助模制（FAM）工艺同时进行，并且在低于执行FAM所需的温度的环境温度下，在FAM之后进行沉积操作。

公开(公告)号：US09425124B2

公开(公告)日：2016-08-23

申请号：US13364907

申请日：2012-02-02

申请人： John P. Karidis ,  Mark D. Schultz

发明人： John P. Karidis ,  Mark D. Schultz

IPC分类号： H01L23/367 ,  H01L23/473 ,  H01L23/00 ,  H01L23/467 ,  H01L21/48

CPC分类号： H01L23/473 ,  B23K1/0014 ,  B23K31/02 ,  B23K2101/14 ,  H01L21/4882 ,  H01L21/4885 ,  H01L23/3677 ,  H01L23/467 ,  H01L24/72 ,  H01L2924/01322 ,  H01L2924/00

摘要： A heat sink includes a plurality of layers being disposed substantially parallel with a surface of a heat source. The layers include a plurality of pin portions spaced apart from each other in a planar arrangement wherein the pin portions of the layers are stacked and bonded to form pin fins extending in a transverse direction relative to the heat source to sink heat. A compliant layer is disposed between the pin fins and a mechanical load. The compliant layer provides compliance such that the pin fins accommodate dimensional differences when interfacing with the heat source.

摘要翻译： 散热器包括与热源的表面基本平行的多个层。 这些层包括以平面布置彼此间隔开的多个销部分，其中层的销部分被堆叠并结合以形成相对于热源在横向方向上延伸以散热的销散热片。 柔性层设置在销散热片和机械负载之间。 顺应层提供顺应性，使得当与热源接合时，销翅片适应尺寸差异。

公开(公告)号：US20160197050A1

公开(公告)日：2016-07-07

申请号：US15071545

申请日：2016-03-16

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Toshihiko AKIBA ,  Akihiro TOBITA ,  Yuki YAGYU

IPC分类号： H01L23/00 ,  H01L21/66

CPC分类号： H01L24/05 ,  H01L21/4885 ,  H01L22/14 ,  H01L22/32 ,  H01L24/03 ,  H01L24/29 ,  H01L24/32 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/02166 ,  H01L2224/0382 ,  H01L2224/03831 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05555 ,  H01L2224/05578 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05673 ,  H01L2224/05684 ,  H01L2224/16012 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/8501 ,  H01L2224/85375 ,  H01L2224/97 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/013 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

摘要： A manufacturing method of a BGA, includes the steps of: providing a semiconductor chip having electrode pads; and removing a natural oxide film formed on the surface of each of the electrode pads. Further, a first film comprised of a conductive member is formed on the surface of the electrode pad exposed by removing the natural oxide film, a wire is connected with the first film, and part of the wire is brought into contact with the electrode pad to form an alloy layer at the interface between the wire and the electrode pad. The crystal structure of the first film is comprised of a body-centered cubic lattice or a hexagonal close-packed lattice. The cost of the semiconductor device can be reduced while the bonding reliability of wire bonding of the semiconductor device is ensured.

公开(公告)号：US09305942B2

公开(公告)日：2016-04-05

申请号：US13703499

申请日：2012-09-21

申请人： BOE TECHNOLOGY GROUP CO., LTD.

发明人： Xiang Liu ,  Jianshe Xue

IPC分类号： G02F1/1362 ,  H01L27/112 ,  H01L29/417 ,  H01L21/02 ,  H01L29/66 ,  H01L27/12 ,  H01L21/04 ,  H01L21/48 ,  H01L27/115 ,  H01L29/45 ,  H01L21/44 ,  H01L27/15

CPC分类号： H01L27/124 ,  G02F1/1362 ,  G02F1/136286 ,  G02F2001/136218 ,  G02F2001/136236 ,  H01L21/44 ,  H01L21/4885 ,  H01L27/1259 ,  H01L27/1288 ,  H01L27/156 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66765

摘要： Embodiments of the present invention provide a TFT array substrate and a method for manufacturing the same and a display device. The TFT array substrate comprises: a base substrate; gate lines, gate electrodes, a gate insulating layer and a semiconductor active layer formed on the base substrate; a metal barrier layer formed on the semiconductor active layer, the metal barrier layer covering the semiconductor active layer; source electrodes and drain electrodes formed on the metal barrier layer, with a metal oxide part being formed between the source electrode and the drain electrode to insulate the source electrode and the drain electrode from each other; and a protection layer formed on the gate insulating layer and the source and drain electrodes, wherein the metal oxide part is formed by oxidizing a part of the metal barrier layer located between the source electrode and the drain electrode.

摘要翻译： 本发明的实施例提供一种TFT阵列基板及其制造方法以及显示装置。 TFT阵列基板包括：基底基板; 栅极线，栅电极，栅绝缘层和形成在基底基板上的半导体有源层; 形成在所述半导体有源层上的金属阻挡层，所述金属阻挡层覆盖所述半导体有源层; 源电极和漏电极，形成在金属阻挡层上，金属氧化物部分形成在源电极和漏电极之间，以使源电极和漏极彼此绝缘; 以及形成在所述栅极绝缘层和所述源极和漏极上的保护层，其中所述金属氧化物部分通过氧化位于所述源电极和所述漏极之间的所述金属阻挡层的一部分而形成。

公开(公告)号：US20150333030A1

公开(公告)日：2015-11-19

申请号：US14711014

申请日：2015-05-13

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Toshihiko AKIBA ,  Akihiro TOBITA ,  Yuki YAGYU

IPC分类号： H01L23/00

CPC分类号： H01L24/05 ,  H01L21/4885 ,  H01L22/14 ,  H01L22/32 ,  H01L24/03 ,  H01L24/29 ,  H01L24/32 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/02166 ,  H01L2224/0382 ,  H01L2224/03831 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05555 ,  H01L2224/05578 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05673 ,  H01L2224/05684 ,  H01L2224/16012 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/8501 ,  H01L2224/85375 ,  H01L2224/97 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/013 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

摘要： A manufacturing method of a BGA, includes the steps of: providing a semiconductor chip having electrode pads; and removing a natural oxide film formed on the surface of each of the electrode pads. Further, a first film comprised of a conductive member is formed on the surface of the electrode pad exposed by removing the natural oxide film, a wire is connected with the first film, and part of the wire is brought into contact with the electrode pad to form an alloy layer at the interface between the wire and the electrode pad. The crystal structure of the first film is comprised of a body-centered cubic lattice or a hexagonal close-packed lattice. The cost of the semiconductor device can be reduced while the bonding reliability of wire bonding of the semiconductor device is ensured.

摘要翻译： 一种BGA的制造方法，包括以下步骤：提供具有电极焊盘的半导体芯片; 并除去形成在每个电极焊盘的表面上的自然氧化膜。 此外，在通过去除天然氧化物膜而暴露的电极焊盘的表面上形成由导电部件构成的第一膜，电线与第一膜连接，并且电线的一部分与电极焊盘接触， 在导线和电极焊盘之间的界面处形成合金层。 第一膜的晶体结构由体心立方晶格或六方密堆积晶格组成。 可以降低半导体器件的成本，同时确保半导体器件的引线接合的接合可靠性。

公开(公告)号：US09087815B2

公开(公告)日：2015-07-21

申请号：US14077597

申请日：2013-11-12

申请人： Invensas Corporation

发明人： Belgacem Haba ,  Reynaldo Co ,  Rizza Lee Saga Cizek ,  Wael Zohni

IPC分类号： B23K31/02 ,  H01L23/00 ,  B23K20/00

CPC分类号： H01L24/43 ,  B23K20/004 ,  B23K20/005 ,  B23K20/007 ,  B23K2101/42 ,  H01L21/4885 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/48 ,  H01L24/85 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/432 ,  H01L2224/4382 ,  H01L2224/43985 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/78301 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2224/45099 ,  H01L2924/00012

摘要： An electrically conductive lead is formed using a bonding tool. After bonding the wire to a metal surface and extending a length of the wire beyond the bonding tool, the wire is clamped. Movement of the bonding tool imparts a kink to the wire at a location where the wire is fully separated from any metal element other than the bonding tool. A forming element, e.g., an edge or a blade skirt provided at an exterior surface of the bonding tool can help kink the wire. Tensioning the wire using the bonding tool causes the wire to break and define an end. The lead then extends from the metal surface to the end.

摘要翻译： 使用接合工具形成导电引线。 在将金属丝接合到金属表面上并将一段长度的金属丝延伸超过粘合工具之后，线被夹紧。 焊接工具的移动在电线与除了焊接工具之外的任何金属元件完全分离的位置处对电线施加扭结。 形成元件，例如设置在接合工具的外表面处的边缘或叶片裙部可以帮助扭结线。 使用接合工具拉紧电线会使电线断裂并确定端部。 然后，引线从金属表面延伸到末端。