公开(公告)号：US20160247719A1

公开(公告)日：2016-08-25

申请号：US15146187

申请日：2016-05-04

申请人： Macronix International Co., Ltd.

发明人： Kuan-Chih Chen ,  Cheng-Wei Lin ,  Kuang-Wen Liu

IPC分类号： H01L21/768 ,  H01L23/528 ,  H01L29/66 ,  H01L23/522 ,  H01L29/792 ,  H01L21/28 ,  H01L23/532

CPC分类号： H01L21/76889 ,  H01L21/26506 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53266 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/456 ,  H01L29/66833 ,  H01L29/792

摘要： Provided are improved semiconductor memory devices and method for manufacturing such semiconductor memory devices. A method may incorporate the formation of silicide regions in a semiconductor. The method may allow for a semiconductor with a silicide layer with improved resistance and reduced silicide bridge formation.

摘要翻译： 提供了用于制造这种半导体存储器件的改进的半导体存储器件和方法。 一种方法可以包括在半导体中形成硅化物区域。 该方法可以允许具有改善的电阻和减少的硅化物桥形成的具有硅化物层的半导体。

公开(公告)号：US09385005B2

公开(公告)日：2016-07-05

申请号：US13704614

申请日：2012-12-14

申请人： Fudan University

发明人： Dongping Wu ,  Zhaoyang Pi ,  Na Zhao ,  Wei Zhang ,  Shi-Li Zhang

IPC分类号： H01L21/4763 ,  H01L21/48 ,  H01L21/768 ,  H01L29/45 ,  H01L23/485 ,  H01L23/532

CPC分类号： H01L21/486 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76883 ,  H01L21/76889 ,  H01L23/485 ,  H01L23/53271 ,  H01L29/458 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure is related to semiconductor technologies and discloses a semiconductor device and its method of making. In the present disclosure, a transistor's source and drain are led out by forming vias or contact holes in an insulator layer covering the transistor and at metal silicide contact regions corresponding to the source and drain, and by filling the vias with metal-semiconductor compound. Because the metal-semiconductor compound has relatively low resistivity, the resistance of the material in the vias can be minimized. Also, because the material used to fill the vias and the material forming the source/drain contact regions are both metal-semiconductor compound, contact resistance between the material filling the vias and the source/drain contact regions can be minimized. Furthermore, because the material filling the vias is metal-semiconductor compound, the conducting material in the vias and dielectric material in the insulator layer can form good interface and have good adhesion properties, and the conducting material would not cause structural damage in the dielectric material. Thus, there is no need to form a barrier layer between the insulator layer and the material filling the vias.

摘要翻译： 本公开涉及半导体技术，并公开了一种半导体器件及其制造方法。 在本公开内容中，通过在覆盖晶体管的绝缘体层和对应于源极和漏极的金属硅化物接触区域处形成通孔或接触孔，并且通过用金属半导体化合物填充通孔来引出晶体管的源极和漏极。 因为金属 - 半导体化合物具有相对较低的电阻率，所以可以使过孔中的材料的电阻最小化。 此外，由于用于填充通孔的材料和形成源极/漏极接触区域的材料都是金属 - 半导体化合物，所以填充通孔的材料与源极/漏极接触区域之间的接触电阻可以最小化。 此外，由于填充过孔的材料是金属 - 半导体化合物，所以绝缘体层中的通孔和电介质材料中的导电材料可以形成良好的界面并且具有良好的粘合性能，并且导电材料不会在介电材料中引起结构损坏 。 因此，不需要在绝缘体层和填充通孔的材料之间形成阻挡层。

公开(公告)号：US20160190014A1

公开(公告)日：2016-06-30

申请号：US14730614

申请日：2015-06-04

申请人： GLOBALFOUNDRIES Inc.

发明人： Suraj K. PATIL ,  Min-hwa CHI

IPC分类号： H01L21/8234 ,  H01L21/324 ,  H01L21/225 ,  H01L21/283

CPC分类号： H01L21/823443 ,  H01L21/2253 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/283 ,  H01L21/285 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/76889 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823835 ,  H01L21/823842

摘要： Methods are provided for fabricating multi-layer semiconductor structures. The methods include, for example: providing a first layer and a second layer over a substrate, the first layer including a first metal and the second layer including a second metal, where the second layer is disposed over the first layer and the first metal and second metal are different metals; and annealing the first layer, the second layer, and the substrate to react at least a portion of the first metal of the first layer to form a first reacted layer and at least a portion of the second metal of the second layer to form a second reacted layer, where at least one of the first reacted layer or the second reacted layer includes at least one of a first metal silicide of the first metal or a second metal silicide of the second metal.

摘要翻译： 提供了制造多层半导体结构的方法。 所述方法包括例如：在衬底上提供第一层和第二层，第一层包括第一金属，第二层包括第二金属，其中第二层设置在第一层和第一金属之上， 第二种金属是不同的金属; 以及退火所述第一层，所述第二层和所述衬底以使所述第一层的所述第一金属的至少一部分反应以形成第一反应层和所述第二层的所述第二金属的至少一部分，以形成第二层 其中第一反应层或第二反应层中的至少一个包含第一金属的第一金属硅化物或第二金属的第二金属硅化物中的至少一种。

公开(公告)号：US09293579B2

公开(公告)日：2016-03-22

申请号：US14284808

申请日：2014-05-22

申请人： INTEL CORPORATION

发明人： Bernhard Sell ,  Oleg Golonzka

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L29/78 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66

CPC分类号： H01L23/535 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53266 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/4925 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an IID disposed on a top surface of a metal gate disposed on the substrate.

公开(公告)号：US20160079250A1

公开(公告)日：2016-03-17

申请号：US14645793

申请日：2015-03-12

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Yoshihiro AKUTSU ,  Ryota Katsumata

IPC分类号： H01L27/115 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L27/11556 ,  H01L21/743 ,  H01L21/76889 ,  H01L23/535 ,  H01L25/00 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.

摘要翻译： 该非易失性半导体存储器件包括存储单元阵列，该存储单元阵列包括在与半导体衬底的表面垂直的第一方向上形成的NAND单元单元。 局部源极线电耦合到形成在衬底表面上的NAND单元单元的一端。 存储单元阵列包括：层叠体，其中将要控制存储单元的栅极线的多个导电膜或选择晶体管的选择栅极线层叠夹层层间绝缘膜; 半导体层，其沿所述第一方向延伸; 以及夹在所述半导体层和所述导电膜之间的电荷蓄积层。 本地源极线包括硅化物层。 电荷累积层由存储单元阵列连续地形成以覆盖硅化物层的周边区域。

公开(公告)号：US20160064277A1

公开(公告)日：2016-03-03

申请号：US14674332

申请日：2015-03-31

申请人： Samsung Electronics Co., Ltd.

发明人： Hyun PARK ,  Dong-Hyun Im ,  Soon-Gun Lee ,  Jong-Myeong Lee ,  Han-Jin Lim

IPC分类号： H01L21/768 ,  H01L49/02

CPC分类号： H01L21/76837 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/02645 ,  H01L21/02653 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76844 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76889 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10855 ,  H01L28/91 ,  H01L29/413 ,  H01L2221/1094

摘要： Methods of fabricating a semiconductor device may include forming guide patterns exposing base patterns, forming first nanowires on the base patterns by performing a first nanowire growth process, forming a first molding insulating layer between the first nanowires, forming holes exposing surfaces of the base patterns by removing the nanowires, and forming first electrodes including a conductive material in the holes.

摘要翻译： 制造半导体器件的方法可以包括形成引导图案，其暴露基底图案，通过执行第一纳米线生长工艺在基底图案上形成第一纳米线，在第一纳米线之间形成第一模制绝缘层， 去除纳米线，并在孔中形成包括导电材料的第一电极。

公开(公告)号：US20160049332A1

公开(公告)日：2016-02-18

申请号：US14457708

申请日：2014-08-12

申请人： GLOBALFOUNDRIES Inc.

发明人： Ruilong Xie ,  Vimal Kamineni ,  William J. Taylor, JR.

IPC分类号： H01L21/768 ,  H01L23/535

CPC分类号： H01L29/4975 ,  H01L21/28525 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/535 ,  H01L29/41758 ,  H01L29/78 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

摘要： One method disclosed herein includes, among other things, a method of forming a contact structure to a source/drain region of a transistor device. The transistor device includes a gate structure and a gate cap layer positioned above the gate structure. The method includes forming an extended-height epi contact structure that is conductively coupled to the source/drain region. The extended-height epi contact structure includes an upper surface that is positioned at a height level that is above a height level of an upper surface of the gate cap layer. The method further includes performing an etching process to trim at least a lateral width of a portion of the extended-height epi contact structure, and, after performing the etching process, forming a metal silicide material on at least a portion of the trimmed extended-height epi contact structure and forming a conductive contact on the metal silicide material.

摘要翻译： 本文公开的一种方法包括形成与晶体管器件的源极/漏极区域的接触结构的方法。 晶体管器件包括栅极结构和位于栅极结构上方的栅极帽层。 该方法包括形成导电耦合到源极/漏极区的扩展高度外延接触结构。 所述延伸高度外延接触结构包括位于所述栅极盖层的上表面的高度以上的高度水平处的上表面。 该方法还包括执行蚀刻工艺以修剪延伸高度外延接触结构的一部分的至少横向宽度，并且在执行蚀刻工艺之后，在修剪的延伸高度外延接触结构的至少一部分上形成金属硅化物材料， 高度epi接触结构，并在金属硅化物材料上形成导电接触。

公开(公告)号：US20160005649A1

公开(公告)日：2016-01-07

申请号：US14737293

申请日：2015-06-11

申请人： ASM International N.V.

发明人： Suvi P. Haukka ,  Antti Niskanen ,  Marko Tuominen

IPC分类号： H01L21/768

CPC分类号： H01L21/7685 ,  C23C16/04 ,  C23C16/14 ,  C23C16/45536 ,  C23C16/45553 ,  H01L21/02068 ,  H01L21/28518 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/3105 ,  H01L21/76826 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76883 ,  H01L21/76886 ,  H01L21/76889 ,  H01L23/53238

摘要： Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic layers are selectively deposited on copper instead of insulating or dielectric materials. In some embodiments, a first precursor forms a layer on the first surface and is subsequently reacted or converted to form a metallic layer. The deposition temperature may be selected such that a selectivity of above about 50% or even about 90% is achieved.

公开(公告)号：US09224645B2

公开(公告)日：2015-12-29

申请号：US13980998

申请日：2011-09-09

申请人： Jun-ichi Ohno

发明人： Jun-ichi Ohno

IPC分类号： H01L21/768 ,  H01L23/482 ,  H01L21/04 ,  H01L29/45 ,  H01L29/66 ,  H01L29/872 ,  H01L21/3065 ,  H01L29/16 ,  H01L29/861

CPC分类号： H01L21/76889 ,  H01L21/0485 ,  H01L21/0495 ,  H01L21/3065 ,  H01L23/4827 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/6606 ,  H01L29/66143 ,  H01L29/8611 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

摘要： A silicon carbide semiconductor device includes: a silicon carbide layer, a reaction layer which is in contact with the silicon carbide layer, a conductive oxidation layer which is in contact with the reaction layer, and an electrode layer which is formed over the reaction layer with the conductive oxidation layer interposed therebetween. A thickness of the conductive oxidation layer falls within a range of 0.3 nm to 2.25 nm.

摘要翻译： 碳化硅半导体器件包括：碳化硅层，与碳化硅层接触的反应层，与反应层接触的导电氧化层，和形成在反应层上的电极层， 导电氧化层插入其间。 导电氧化层的厚度在0.3nm〜2.25nm的范围内。

公开(公告)号：US20150364488A1

公开(公告)日：2015-12-17

申请号：US14734254

申请日：2015-06-09

申请人： SANDISK TECHNOLOGIES, INC.

发明人： Jayavel PACHAMUTHU ,  Yingda DONG ,  Johann ALSMEIER

IPC分类号： H01L27/115 ,  H01L21/768 ,  H01L23/532 ,  H01L21/02 ,  H01L23/528

CPC分类号： H01L27/11582 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/76886 ,  H01L21/76889 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53219 ,  H01L23/53233 ,  H01L23/53261 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/665 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory device and a method of making a memory device that includes a stack of alternating layers of a first material and a second material different from the first material over a substrate, where the layers of the second material form a plurality of conductive control gate electrodes. A plurality of NAND memory strings extend through the stack, where each NAND memory string includes a semiconductor channel which contains at least a first portion which extends substantially perpendicular to a major surface of the substrate and at least one memory film located between the semiconductor channel and the plurality of conductive control gate electrodes. A source line including a metal silicide material extends through the stack.

摘要翻译： 一种存储器件和制造存储器件的方法，所述存储器件包括在衬底上的第一材料和不同于第一材料的第二材料的交替层的堆叠，其中第二材料的层形成多个导电控制栅电极 。 多个NAND存储器串延伸通过堆栈，其中每个NAND存储器串包括半导体通道，该半导体通道至少包含基本上垂直于衬底主表面延伸的第一部分和位于半导体通道和 多个导电控制栅电极。 包括金属硅化物材料的源极线延伸穿过堆叠。