公开(公告)号：US07622737B2

公开(公告)日：2009-11-24

申请号：US11776114

申请日：2007-07-11

Applicant: Mukta G. Farooq ,  Xiao H. Liu ,  Ian D. Melville

Inventor： Mukta G. Farooq ,  Xiao H. Liu ,  Ian D. Melville

IPC: H01L23/58 ,  H01L21/00

CPC classification number: G01R31/2853 ,  H01L22/34 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00012

Abstract: Test structures for electrically detecting BEOL failures are provided. In an embodiment, the structure comprises: an input/output connection disposed above a primary conductive pad which is embedded in an insulator; a dielectric layer disposed upon the insulator; a primary via extending through the dielectric layer down to the primary conductive pad for providing electrical connection between the input/output connection and the primary conductive pad; and a secondary via filled with a conductive material in electrical connection with the input/output connection, the secondary via extending through the dielectric layer down to a secondary interconnect in electrical connection with a secondary conductive pad that is insulated from the primary conductive pad.

Abstract translation: 提供电气检测BEOL故障的测试结构。 在一个实施例中，该结构包括：输入/输出连接，其布置在嵌入绝缘体中的主导电垫上方; 设置在绝缘体上的电介质层; 主通孔延伸穿过介电层到主导电焊盘，用于在输入/输出连接和主导电焊盘之间提供电连接; 以及填充有与所述输入/输出连接电连接的导电材料的次级通孔，所述次级通孔延伸穿过所述电介质层到与所述主导电焊盘绝缘的次级导电焊盘电连接的次互连。

公开(公告)号：US20080029898A1

公开(公告)日：2008-02-07

申请号：US11461511

申请日：2006-08-01

Applicant: Mukta G. Farooq ,  Robert Hannon ,  Dae Young Jung ,  Ian D. Melville ,  Donna S. Zupanski-Nielsen

Inventor： Mukta G. Farooq ,  Robert Hannon ,  Dae Young Jung ,  Ian D. Melville ,  Donna S. Zupanski-Nielsen

IPC: H01L23/48

CPC classification number: H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Via stack structures are disclosed. In one embodiment, a structure includes a via stack including: a first substantially cross-shaped line in a first dielectric layer; a second substantially cross-shaped line set in a second dielectric layer, and a via stud coupling the first substantially cross-shaped line to the second substantially cross-shaped line. In another embodiment, a structure includes a first via stack, and a second via stack, wherein the first via stack and the second via stack extend in a divergent manner from one another. Each via stack structure is useful for support, for example, in under wire bond applications. The via stack structures can be mixed with other via stack structures and selectively placed within a layout to replace conventional metal plate and via stud array configurations.

Abstract translation: 公开了通过堆叠结构。 在一个实施例中，结构包括通孔堆叠，其包括：第一介电层中的第一基本十字形的线; 设置在第二电介质层中的第二基本上十字形的线，以及将第一基本上十字形的线耦合到第二基本十字形线的通孔柱。 在另一个实施例中，结构包括第一通孔堆叠和第二通孔堆叠，其中第一通孔堆叠和第二通孔堆叠以彼此发散的方式延伸。 每个通孔堆叠结构可用于支持，例如在引线键合应用中。 通孔堆叠结构可以与其它通孔堆叠结构混合并且选择性地放置在布局内以代替传统的金属板和经由螺柱阵列配置。

公开(公告)号：US09069923B2

公开(公告)日：2015-06-30

申请号：US13161514

申请日：2011-06-16

Applicant: Soon Yoeng Tan ,  Teck Jung Tang ,  Ian D. Melville ,  Yelei Vianna Yao ,  Yasushi Yamagata

Inventor： Soon Yoeng Tan ,  Teck Jung Tang ,  Ian D. Melville ,  Yelei Vianna Yao ,  Yasushi Yamagata

IPC: G06F17/50 ,  G06F7/06 ,  G06F1/00 ,  H01L29/66

CPC classification number: H01L27/0207 ,  G06F17/5068 ,  G06F2217/66 ,  H01L22/32

Abstract: Multi-Project Wafers includes a plurality of chiplets from different IP owners. Non-relevant chiplets are implemented with IP protection to inhibit IP disclosure of non-relevant IP owners.

Abstract translation: 多项目晶片包括来自不同IP所有者的多个小芯片。 采用知识产权保护措施实施不相关的小白鼠，以防止非相关知识产权拥有者的知识产权披露。

公开(公告)号：US08999764B2

公开(公告)日：2015-04-07

申请号：US11836819

申请日：2007-08-10

Applicant: Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca ,  Kenneth P. Rodbell

Inventor： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca ,  Kenneth P. Rodbell

IPC: H01L21/00 ,  H01L23/532 ,  H01L23/556

CPC classification number: H01L23/5329 ,  H01L23/556 ,  H01L2924/0002 ,  Y10S438/958 ,  Y10S438/967 ,  H01L2924/00

Abstract: Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.

Abstract translation: 公开了阻止电离辐射以减少软错误的方法和产生的IC芯片。 一个实施例包括形成用于集成电路（IC）芯片的线路前端（FEOL）; 以及在其中形成包括其中的电离辐射阻挡材料的至少一个后端线（BEOL）电介质层。 另一实施例包括形成用于集成电路（IC）芯片的线路前端（FEOL）; 以及形成位于IC芯片的后端（BEOL）的电离辐射阻挡层。 电离辐射阻挡材料或层吸收电离辐射并减少IC芯片内的软误差。

公开(公告)号：US20120168956A1

公开(公告)日：2012-07-05

申请号：US12984069

申请日：2011-01-04

Applicant: Stephane S. Barbeau ,  Catherine C. Dufort ,  Ian D. Melville ,  Luc L. Ouellet ,  Marie-Claude Paquet ,  Wolfgang Sauter ,  Jeffrey S. Zimmerman

Inventor： Stephane S. Barbeau ,  Catherine C. Dufort ,  Ian D. Melville ,  Luc L. Ouellet ,  Marie-Claude Paquet ,  Wolfgang Sauter ,  Jeffrey S. Zimmerman

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L24/83 ,  H01L21/563 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/94 ,  H01L2224/131 ,  H01L2224/16235 ,  H01L2224/2929 ,  H01L2224/29388 ,  H01L2224/325 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/8312 ,  H01L2224/83855 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00

Abstract: A method forms an integrated circuit structure, using a manufacturing device, to have kerf regions and external contacts, and to have conductive structures in the kerf regions. The method also forms an underfill material on a surface of the integrated circuit structure, using the manufacturing device, that contacts the kerf regions and the external contacts. The underfill material comprises electrically attracted filler particles that affect the coefficient of thermal expansion and elastic modulus of the underfill material. When forming the underfill material, the method applies an electrical charge to the conductive structures and the external contacts.

Abstract translation: 一种方法使用制造装置形成集成电路结构，以具有切口区域和外部触点，并且在切口区域中具有导电结构。 该方法还使用与切口区域和外部接触件接触的制造装置在集成电路结构的表面上形成底部填充材料。 底部填充材料包括影响底部填充材料的热膨胀系数和弹性模量的电吸引填料颗粒。 当形成底部填充材料时，该方法对导电结构和外部触点施加电荷。

公开(公告)号：US20120168952A1

公开(公告)日：2012-07-05

申请号：US13418261

申请日：2012-03-12

Applicant: Mukta G. Farooq ,  Emily R. Kinser ,  Ian D. Melville ,  Krystyna W. Semkow

Inventor： Mukta G. Farooq ,  Emily R. Kinser ,  Ian D. Melville ,  Krystyna W. Semkow

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L21/02697 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05007 ,  H01L2224/05016 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05187 ,  H01L2224/05562 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/15787 ,  H01L2924/04953 ,  H01L2924/01014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Disclosed is a process of making a semiconductor device wherein an insulation layer has a copper plug in contact with the last wiring layer of the device. There may also be a barrier layer separating the copper plug from the insulation layer. There may also be a cap layer over the copper plug to protect it from oxidation. There may also be a dielectric layer over the cap layer.

Abstract translation: 公开了制造半导体器件的方法，其中绝缘层具有与器件的最后布线层接触的铜插塞。 还可以存在将铜塞与绝缘层分离的阻挡层。 在铜塞上方也可能有一个盖层，以防止它被氧化。 在盖层上还可以存在介电层。

公开(公告)号：US08022543B2

公开(公告)日：2011-09-20

申请号：US12054713

申请日：2008-03-25

Applicant: Mukta G. Farooq ,  Robert Hannon ,  Emily R. Kinser ,  Ian D. Melville

Inventor： Mukta G. Farooq ,  Robert Hannon ,  Emily R. Kinser ,  Ian D. Melville

IPC: H01L23/48

CPC classification number: H01L24/11 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/05552 ,  H01L2924/00014 ,  H01L2924/013

Abstract: A first metallic diffusion barrier layer is formed on a last level metal plate exposed in an opening of a passivation layer. Optionally, a metallic adhesion promotion layer is formed on the first metallic diffusion barrier layer. An elemental metal conductive layer is formed on the metallic adhesion promotion layer, which provides a highly conductive structure that distributes current uniformly due to the higher electrical conductivity of the material than the layers above or below. A stack of the second metallic diffusion barrier layer and a wetting promotion layer is formed, on which a C4 ball is bonded. The elemental metal conductive layer distributes the current uniformly within the underbump metallurgy structure, which induces a more uniform current distribution in the C4 ball and enhanced electromigration resistance of the C4 ball.

Abstract translation: 第一金属扩散阻挡层形成在暴露在钝化层的开口中的最后一级金属板上。 任选地，在第一金属扩散阻挡层上形成金属粘附促进层。 在金属粘合促进层上形成元素金属导电层，其提供高导电性结构，其由于材料的导电性高于或高于上述层而导致电流均匀分布。 形成第二金属扩散阻挡层和润湿促进层的叠层，其上结合有C4球。 元素金属导电层将电流均匀分布在下焊管冶金结构内，从而在C4球中引起更均匀的电流分布，提高C4球的电迁移阻力。

公开(公告)号：US07919356B2

公开(公告)日：2011-04-05

申请号：US11831026

申请日：2007-07-31

Applicant: Mukta G. Farooq ,  Robert Hannon ,  Dae-Young Jung ,  Ian D. Melville

Inventor： Mukta G. Farooq ,  Robert Hannon ,  Dae-Young Jung ,  Ian D. Melville

IPC: H01L21/44

CPC classification number: H01L21/563 ,  H01L24/32 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/26145 ,  H01L2224/29036 ,  H01L2224/321 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/831 ,  H01L2224/83379 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2224/05599

Abstract: A method of assembling a microelectronic flip-chip arrangement includes attaching a chip having a defined length to a supporting substrate, wherein the chip forms a chip shadow line of the defined length on the supporting substrate, creating a first non-wettable zone on an outer portion of the bottom surface of the chip, creating a second non-wettable zone on a portion of the supporting substrate outside the chip shadow line, underfilling the chip and forming a fillet, wherein the fillet does not extend beyond the chip shadow line, and hardening the underfill including the fillet.

Abstract translation: 组装微电子倒装芯片布置的方法包括将具有限定长度的芯片附接到支撑衬底，其中芯片在支撑衬底上形成具有限定长度的芯片阴影线，在外部形成第一非可湿润区域 在芯片阴影线外部的支撑基板的一部分上形成第二不可润湿区域，在芯片上填充并形成圆角，其中圆角不延伸超过芯片阴影线，以及 硬化底部填充物，包括圆角。

公开(公告)号：US07816248B2

公开(公告)日：2010-10-19

申请号：US12138482

申请日：2008-06-13

Applicant: Mukta G. Farooq ,  Lacrtis Economikos ,  Ian D. Melville ,  Kevin S. Petrarca ,  Richard P. Volant

Inventor： Mukta G. Farooq ,  Lacrtis Economikos ,  Ian D. Melville ,  Kevin S. Petrarca ,  Richard P. Volant

IPC: H01L21/44

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05085 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: Disclosed are embodiments of a far back end of the line solder connector and a method of forming the connector that eliminates the use aluminum, protects the integrity of the ball limiting metallurgy (BLM) layers and promotes adhesion of the BLM layers by incorporating a thin conformal conductive liner into the solder connector structure. This conductive liner coats the top of the via filling in any divots in order to create a uniform surface for BLM deposition and to, thereby, protect the integrity of the BLM layers. The liner further coats the dielectric sidewalls of the well in which the BLM layers are formed in order to enhance adhesion of the BLM layers to the well.

Abstract translation: 公开了线焊料连接器的远端的实施例以及形成连接器的方法，其消除了使用铝，保护了球限制冶金（BLM）层的完整性，并且通过并入薄的保形膜来促进BLM层的粘附 导电衬里进入焊接接头结构。 该导电衬里以通孔填充物的顶部涂覆任何刻痕，以便产生用于BLM沉积的均匀表面，从而保护BLM层的完整性。 衬垫还涂覆在其中形成BLM层的阱的电介质侧壁，以便增强BLM层与阱的粘合性。

公开(公告)号：US07648891B2

公开(公告)日：2010-01-19

申请号：US11615236

申请日：2006-12-22

Applicant: Mukta G. Farooq ,  Dae-Young Jung ,  Ian D. Melville

Inventor： Mukta G. Farooq ,  Dae-Young Jung ,  Ian D. Melville

IPC: H01L21/78

CPC classification number: H01L21/67092 ,  H01L21/78 ,  H01L23/562 ,  H01L29/0657 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention is directed to an improved semiconductor chip that reduces crack initiation and propagation into the active area of a semiconductor chip. A semiconductor wafer includes dicing channels that separate semiconductor chips and holes through a portion of a semiconductor chip, which are located at the intersection of the dicing channels. Once diced from the semiconductor wafer, semiconductor chips are created without ninety degree angle corners.

Abstract translation: 本发明涉及一种改进的半导体芯片，其减少裂纹发生和传播到半导体芯片的有源区域。 半导体晶片包括分开半导体芯片和穿过半导体芯片的位于切割通道的交叉点的部分的切割通道。 一旦从半导体晶片切割，半导体芯片就不会产生90度角角。