公开(公告)号：US20160035586A1

公开(公告)日：2016-02-04

申请号：US14448901

申请日：2014-07-31

Applicant: APPLIED MATERIALS, INC.

Inventor： Vinod R. Purayath ,  Randhir Thakur ,  Shankar Venkataraman ,  Nitin K. Ingle

IPC: H01L21/3213 ,  H01L21/677 ,  H01L29/423 ,  H01L21/28 ,  H01L29/40

CPC classification number: H01L21/32137 ,  H01J37/32357 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/28273 ,  H01L21/31116 ,  H01L21/67739 ,  H01L21/76224 ,  H01L29/401 ,  H01L29/42324 ,  H01L29/66825

Abstract: Methods of etching back shallow trench isolation (STI) dielectric and trimming the exposed floating gate without breaking vacuum are described. The methods include recessing silicon oxide dielectric gapfill to expose vertical sidewalls of polysilicon floating gates. The exposed vertical sidewalls are then isotropically etched to evenly thin the polysilicon floating gates on the same substrate processing mainframe. Both recessing silicon oxide and isotropically etching polysilicon use remotely excited fluorine-containing apparatuses attached to the same mainframe to facilitate performing both operations without an intervening atmospheric exposure. An inter-poly dielectric may then be conformally deposited either on the same mainframe or outside the mainframe.

Abstract translation: 描述了在不破坏真空的情况下回蚀浅沟槽隔离（STI）电介质和修整暴露的浮动栅极的方法。 这些方法包括凹陷氧化硅电介质间隙填充以暴露多晶硅浮动栅极的垂直侧壁。 然后对暴露的垂直侧壁进行各向同性蚀刻，以在相同的基板处理主机上均匀地稀薄多晶硅浮动栅极。 凹陷硅氧化物和各向同性蚀刻多晶硅都使用连接在同一主机上的远程激发的含氟设备，以便于在没有中间大气暴露的情况下进行两种操作。 然后可将多晶硅电介质保形地沉积在同一主机上或主机外部。

公开(公告)号：US09144147B2

公开(公告)日：2015-09-22

申请号：US13773067

申请日：2013-02-21

Applicant: Applied Materials, Inc.

Inventor： Jang-Gyoo Yang ,  Matthew L. Miller ,  Xinglong Chen ,  Kien N. Chuc ,  Qiwei Liang ,  Shankar Venkataraman ,  Dmitry Lubomirsky

IPC: C23C16/00 ,  C23F1/00 ,  H01L21/306 ,  H01J37/32 ,  H05H1/24 ,  C23C16/455

CPC classification number: H05H1/24 ,  C23C16/45565 ,  C23C16/45585 ,  H01J37/32091 ,  H01J37/32357 ,  H01J37/32422 ,  H01J37/3244 ,  H01J37/32449 ,  H01J37/32532 ,  H01J37/32541 ,  H01J37/32568 ,  H01J37/32724 ,  H01L21/02274

Abstract: Substrate processing systems are described that have a capacitively coupled plasma (CCP) unit positioned inside a process chamber. The CCP unit may include a plasma excitation region formed between a first electrode and a second electrode. The first electrode may include a first plurality of openings to permit a first gas to enter the plasma excitation region, and the second electrode may include a second plurality of openings to permit an activated gas to exit the plasma excitation region. The system may further include a gas inlet for supplying the first gas to the first electrode of the CCP unit, and a pedestal that is operable to support a substrate. The pedestal is positioned below a gas reaction region into which the activated gas travels from the CCP unit.

Abstract translation: 描述了具有位于处理室内的电容耦合等离子体（CCP）单元的衬底处理系统。 CCP单元可以包括形成在第一电极和第二电极之间的等离子体激发区域。 第一电极可以包括允许第一气体进入等离子体激发区域的第一多个开口，并且第二电极可以包括允许活化气体离开等离子体激发区域的第二多个开口。 该系统还可以包括用于将第一气体供应到CCP单元的第一电极的气体入口和可操作以支撑衬底的基座。 基座位于气体反应区域的下方，活性气体从CCP单元行进。

公开(公告)号：US09023732B2

公开(公告)日：2015-05-05

申请号：US14246937

申请日：2014-04-07

Applicant: Applied Materials, Inc.

Inventor： Anchuan Wang ,  Xinglong Chen ,  Zihui Li ,  Hiroshi Hamana ,  Zhijun Chen ,  Ching-Mei Hsu ,  Jiayin Huang ,  Nitin K. Ingle ,  Dmitry Lubomirsky ,  Shankar Venkataraman ,  Randhir Thakur

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/263 ,  H01L21/677 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/67 ,  H01L21/683 ,  H01J37/32 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/324 ,  C23C16/4405 ,  H01J37/32357 ,  H01J37/32862 ,  H01L21/02041 ,  H01L21/02057 ,  H01L21/0206 ,  H01L21/263 ,  H01L21/2686 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/67069 ,  H01L21/67075 ,  H01L21/6708 ,  H01L21/67109 ,  H01L21/67115 ,  H01L21/67184 ,  H01L21/6719 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/67207 ,  H01L21/67248 ,  H01L21/67253 ,  H01L21/67288 ,  H01L21/67703 ,  H01L21/67739 ,  H01L21/67742 ,  H01L21/6831

Abstract: Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools.

公开(公告)号：US20140273488A1

公开(公告)日：2014-09-18

申请号：US14246978

申请日：2014-04-07

Applicant: APPLIED MATERIALS, INC.

Inventor： Anchuan Wang ,  Xinglong Chen ,  Zihui Li ,  Hiroshi Hamana ,  Zhijun Chen ,  Ching-Mei Hsu ,  Jiayin Huang ,  Nitin K. Ingle ,  Dmitry Lubomirsky ,  Shankar Venkataraman ,  Randhir Thakur

IPC: H01L21/67 ,  H01L21/3065

CPC classification number: H01L21/324 ,  C23C16/4405 ,  H01J37/32357 ,  H01J37/32862 ,  H01L21/02041 ,  H01L21/02057 ,  H01L21/0206 ,  H01L21/263 ,  H01L21/2686 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/67069 ,  H01L21/67075 ,  H01L21/6708 ,  H01L21/67109 ,  H01L21/67115 ,  H01L21/67184 ,  H01L21/6719 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/67207 ,  H01L21/67248 ,  H01L21/67253 ,  H01L21/67288 ,  H01L21/67703 ,  H01L21/67739 ,  H01L21/67742 ,  H01L21/6831

Abstract: Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools.

公开(公告)号：US20140262038A1

公开(公告)日：2014-09-18

申请号：US14246915

申请日：2014-04-07

Applicant: APPLIED MATERIALS, INC.

Inventor： Anchuan Wang ,  Xinglong Chen ,  Zihui Li ,  Hiroshi Hamana ,  Zhijun Chen ,  Ching-Mei Hsu ,  Jiayin Huang ,  Nitin K. Ingle ,  Dmitry Lubomirsky ,  Shankar Venkataraman ,  Randhir Thakur

IPC: H01L21/67

CPC classification number: H01L21/324 ,  C23C16/4405 ,  H01J37/32357 ,  H01J37/32862 ,  H01L21/02041 ,  H01L21/02057 ,  H01L21/0206 ,  H01L21/263 ,  H01L21/2686 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/67069 ,  H01L21/67075 ,  H01L21/6708 ,  H01L21/67109 ,  H01L21/67115 ,  H01L21/67184 ,  H01L21/6719 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/67207 ,  H01L21/67248 ,  H01L21/67253 ,  H01L21/67288 ,  H01L21/67703 ,  H01L21/67739 ,  H01L21/67742 ,  H01L21/6831

Abstract: Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools.

公开(公告)号：US20140227881A1

公开(公告)日：2014-08-14

申请号：US13791074

申请日：2013-03-08

Applicant: Applied Materials, Inc.

Inventor： Dmitry Lubomirsky ,  Xinglong Chen ,  Shankar Venkataraman

IPC: H01L21/67 ,  H01L21/3065

CPC classification number: H01J37/32357 ,  C23C16/45565 ,  C23C16/505 ,  C23C16/54 ,  H01J37/32422 ,  H01J37/32449 ,  H01J37/32899 ,  H01L21/32136 ,  H01L21/67069

Abstract: An exemplary system may include a chamber configured to contain a semiconductor substrate in a processing region of the chamber. The system may include a first remote plasma unit fluidly coupled with a first access of the chamber and configured to deliver a first precursor into the chamber through the first access. The system may still further include a second remote plasma unit fluidly coupled with a second access of the chamber and configured to deliver a second precursor into the chamber through the second access. The first and second access may be fluidly coupled with a mixing region of the chamber that is separate from and fluidly coupled with the processing region of the chamber. The mixing region may be configured to allow the first and second precursors to interact with each other externally from the processing region of the chamber.

Abstract translation: 示例性系统可以包括被配置成在腔室的处理区域中容纳半导体衬底的腔室。 该系统可以包括第一远程等离子体单元，该第一远程等离子体单元与腔室的第一通路流体耦合并且被配置为通过第一通路将第一前体输送到腔室中。 系统还可以包括第二远程等离子体单元，该第二远程等离子体单元与腔室的第二通路流体耦合并且被配置为通过第二通路将第二前体输送到腔室中。 第一和第二通路可以与腔室的混合区域流体耦合，腔室的混合区域与腔室的处理区域分开并与腔室的处理区域流体耦合。 混合区域可以被配置为允许第一和第二前体在室的处理区域外部彼此相互作用。

公开(公告)号：US20130252440A1

公开(公告)日：2013-09-26

申请号：US13623792

申请日：2012-09-20

Applicant: APPLIED MATERIALS, INC.

Inventor： Lei Luo ,  Shankar Venkataraman ,  Manuel A. Hernandez ,  Kedar Sapre ,  Zhong Qiang Hua

IPC: H01L21/02

CPC classification number: H01L21/0226 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02315 ,  H01L21/02362 ,  H01L21/76831 ,  H01L21/76898

Abstract: Methods of conformally depositing silicon oxide layers on patterned substrates are described. The patterned substrates are plasma treated such that subsequently deposited silicon oxide layers may deposit uniformly on walls of deep closed trenches. The technique is particularly useful for through-substrate vias (TSVs) which require especially deep trenches. The trenches may be closed at the bottom and deep to enable through-substrate vias (TSVs) by later removing a portion of the backside substrate (near to the closed end of the trench). The conformal silicon oxide layer thickness on the sidewalls near the bottom of a trench is greater than or about 70% of the conformal silicon oxide layer thickness near the top of the trench in embodiments of the invention. The improved uniformity of the silicon oxide layer enables a subsequently deposited conducting plug to be thicker and offer less electrical resistance.

Abstract translation: 描述了在图案化衬底上共形沉积氧化硅层的方法。 图案化的衬底被等离子体处理，使得随后沉积的氧化硅层可以均匀地沉积在深闭合的沟槽的壁上。 该技术对于需要特别深的沟槽的贯通衬底通孔（TSV）特别有用。 沟槽可以在底部和深处封闭，以便通过稍后去除背面衬底的一部分（靠近沟槽的封闭端）来实现贯穿衬底通孔（TSV）。 在本发明的实施方案中，靠近沟槽底部的侧壁上的共形氧化硅层厚度大于或接近沟槽顶部的共形氧化硅层厚度的约70％。 氧化硅层的改进的均匀性使得随后沉积的导电插头更厚并且提供更少的电阻。

公开(公告)号：US20240420953A1

公开(公告)日：2024-12-19

申请号：US18209719

申请日：2023-06-14

Applicant: Applied Materials, Inc.

Inventor： Rui Lu ,  Bo Xie ,  Wei Liu ,  Shanshan Yao ,  Xiaobo Li ,  Jingmei Liang ,  Li-Qun Xia ,  Shankar Venkataraman ,  Chi-I Lang

IPC: H01L21/02

Abstract: Exemplary processing methods may include providing a treatment precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. The substrate may include a layer of a silicon-containing material. The methods may include forming inductively-coupled plasma effluents of the treatment precursor. The methods may include contacting the layer of the silicon-containing material with the inductively-coupled plasma effluents of the treatment precursor to produce a treated layer of the silicon-containing material. The contacting may reduce a dielectric constant of the layer of the silicon-containing material.

公开(公告)号：US20240363337A1

公开(公告)日：2024-10-31

申请号：US18139699

申请日：2023-04-26

Applicant: Applied Materials, Inc.

Inventor： Muthukumar Kaliappan ,  Bo Xie ,  Shanshan Yao ,  Li-Qun Xia ,  Michael Haverty ,  Rui Lu ,  Xiaobo Li ,  Chi-I Lang ,  Shankar Venkataraman

IPC: H01L21/02 ,  C23C16/32 ,  C23C16/455 ,  C23C16/56

CPC classification number: H01L21/02167 ,  C23C16/325 ,  C23C16/45542 ,  C23C16/45553 ,  C23C16/45565 ,  C23C16/56 ,  H01L21/02211 ,  H01L21/02274

Abstract: Semiconductor processing methods are described for forming low-κ dielectric materials. The methods may include providing deposition precursors to a processing region of a semiconductor processing chamber. The deposition precursors may include a silicon-carbon-and-hydrogen-containing precursor. A substrate may be disposed within the processing region. The methods may include forming plasma effluents of the deposition precursors. The methods may include depositing a layer of silicon-containing material on the substrate. The layer of silicon-containing material may be characterized by a dielectric constant of less than or about 4.0.

公开(公告)号：US10550472B2

公开(公告)日：2020-02-04

申请号：US14481774

申请日：2014-09-09

Applicant: Applied Materials, Inc.

Inventor： Kien N. Chuc ,  Qiwei Liang ,  Hanh D. Nguyen ,  Xinglong Chen ,  Matthew Miller ,  Soonam Park ,  Toan Q. Tran ,  Adib Khan ,  Jang-Gyoo Yang ,  Dmitry Lubomirsky ,  Shankar Venkataraman

IPC: C23C16/455 ,  H01J37/32 ,  C23C16/452

Abstract: Apparatus and methods for gas distribution assemblies are provided. In one aspect, a gas distribution assembly is provided comprising an annular body comprising an annular ring having an inner annular wall, an outer wall, an upper surface, and a bottom surface, an upper recess formed into the upper surface, and a seat formed into the inner annular wall, an upper plate positioned in the upper recess, comprising a disk-shaped body having a plurality of first apertures formed therethrough, and a bottom plate positioned on the seat, comprising a disk-shaped body having a plurality of second apertures formed therethrough which align with the first apertures, and a plurality of third apertures formed between the second apertures and through the bottom plate, the bottom plate sealingly coupled to the upper plate to fluidly isolate the plurality of first and second apertures from the plurality of third apertures.