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公开(公告)号：US09275952B2
公开(公告)日：2016-03-01
申请号：US14162993
申请日：2014-01-24
发明人： Donald F. Canaperi , Daniel C. Edelstein , Alfred Grill , Son V. Nguyen , Takeshi Nogami , Deepika Priyadarshini , Hosadurga Shobha
IPC分类号： H01L23/532 , H01L21/768 , H01L29/872 , H01L29/739
CPC分类号： H01L23/53238 , H01L21/28556 , H01L21/28568 , H01L21/76832 , H01L21/76834 , H01L21/76843 , H01L21/76846 , H01L21/76849 , H01L21/76879 , H01L23/528 , H01L29/7395 , H01L29/872 , H01L2924/0002 , H01L2924/00
摘要： An electrical device including an opening in a low-k dielectric material, and a copper including structure present within the opening for transmitting electrical current. A liner is present between the opening and the copper including structure. The liner includes a superlattice structure comprised of a metal oxide layer, a metal layer present on the metal oxide layer, and a metal nitride layer that is present on the metal layer. A first layer of the superlattice structure that is in direct contact with the low-k dielectric material is one of said metal oxide layer and a final layer of the superlattice structure that is in direct contact with the copper including structure is one of the metal nitride layers.
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公开(公告)号：US20160047038A1
公开(公告)日：2016-02-18
申请号：US14926684
申请日：2015-10-29
发明人： Donald Francis Canaperi , Alfred Grill , Sanjay C. Mehta , Son Van Nguyen , Deepika Priyadarshini , Hosadurga Shobha , Matthew T. Shoudy
IPC分类号： C23C16/455 , C23C16/34 , C23C16/40
CPC分类号： H01L21/02274 , C23C16/345 , C23C16/401 , C23C16/45523 , C23C16/45525 , C23C16/50 , H01L21/02123 , H01L21/02126 , H01L21/0214 , H01L21/02164 , H01L21/02167 , H01L21/0217 , H01L21/022 , H01L21/02211 , H01L21/02214 , H01L21/02219 , H01L21/02299 , H01L21/76832 , H01L21/76834 , H01L23/485 , H01L23/5226 , H01L23/528 , H01L23/53276 , H01L23/5329 , H01L23/53295 , H01L29/42364 , H01L29/4983 , H01L29/511 , H01L29/513 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the present invention provide hydrogen-free dielectric films and methods of fabrication. A hydrogen-free precursor, such as tetraisocyanatosilane, and hydrogen-free reactants, such as nitrogen, oxygen (O2/O3) and nitrous oxide are used with chemical vapor deposition processes (PECVD, thermal CVD, SACVD, HDP CVD, and PE and Thermal ALD) to create hydrogen-free dielectric films. In some embodiments, there are multilayer dielectric films with sublayers of various materials such as silicon oxide, silicon nitride, and silicon oxynitride. In embodiments, the hydrogen-free reactants may include Tetra Isocyanato Silane, along with a hydrogen-free gas including, but not limited to, N2, O2, O3, N2O, CO2, CO and a combination thereof of these H-Free gases. Plasma may be used to enhance the reaction between the TICS and the other H-free gasses. The plasma may be controlled during film deposition to achieve variable density within each sublayer of the films.
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43.发明授权Advanced ultra low k SiCOH dielectrics prepared by built-in engineered pore size and bonding structured with cyclic organosilicon precursors 有权通过内置工程孔径和用循环有机硅前体结构的键合制备的先进的超低k SiCOH电介质公开(公告)号：US09209017B2
公开(公告)日：2015-12-08
申请号：US14225810
申请日：2014-03-26
IPC分类号： H01L21/47 , H01L21/02 , H01B3/46 , H01L23/532
CPC分类号： H01L21/02126 , H01B3/46 , H01L21/02203 , H01L21/02211 , H01L21/02216 , H01L21/02274 , H01L21/0234 , H01L21/02348
摘要： Disclosed herein is an ultra-low dielectric (k) film and methods of making thereof. A ultra-low k film has a covalently bonded network comprising atoms of silicon, oxygen, carbon, and hydrogen, a cyclotrisilane structure, and a plurality of pores having a pore size distribution (PSD) of less than about 1.1 nanometers (nm). The ultra-low k film has a k value of less than about 2.4 and at least about 28 atomic percent of carbon.
摘要翻译： 本文公开了一种超低介电（k）薄膜及其制造方法。 超低k膜具有包含硅，氧，碳和氢的原子，环状硅烷结构和孔径分布（PSD）小于约1.1纳米（nm）的多个孔的共价键合网络。 超低k膜具有小于约2.4的k值和至少约28原子％的碳。
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44.发明申请COMPOSITE DIELECTRIC MATERIALS WITH IMPROVED MECHANICAL AND ELECTRICAL PROPERTIES 有权具有改进的机械和电气特性的复合电介质材料公开(公告)号：US20150270124A1
公开(公告)日：2015-09-24
申请号：US14220288
申请日：2014-03-20
IPC分类号： H01L21/02
CPC分类号： H01L21/02115 , H01L21/02126 , H01L21/02203 , H01L21/02255 , H01L21/02282 , H01L21/7682 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： A low k dielectric material with enhanced electrical and mechanical properties is provided which, in some applications, can also reduce the capacitance of a semiconductor device. The low k dielectric material includes CNT nanotubes that are randomly dispersed within a low k dielectric material matrix. The low k dielectric material can be used in a variety of electronic devices including, for example, as an insulator layer within a back end of line interconnect structure.
摘要翻译： 提供了具有增强的电气和机械性能的低k电介质材料，其在一些应用中也可以降低半导体器件的电容。 低k介电材料包括随机分散在低k电介质材料基体内的CNT纳米管。 低k电介质材料可用于各种电子器件，包括例如在线互连结构的后端中的绝缘体层。
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公开(公告)号：US09028628B2
公开(公告)日：2015-05-12
申请号：US13826229
申请日：2013-03-14
发明人： Wei Lin , Deepika Priyadarshini , Spyridon Skordas , Tuan A. Vo
CPC分类号： H01L21/02 , H01L21/2007 , H01L21/67092
摘要： Oxide-oxide fusion bonding of wafers that includes performing a van der Waals force bonding process with a chuck having at least a flat central zone and an outer annular zone lower than the central zone, an edge portion of a mounted wafer is biased towards the outer annular zone. The van der Waals bonding wave is disrupted at the outer annular zone, causing an edge gap. A thermocompression bonding process is performed that includes heating the bonded wafers to a temperature sufficient to initiate condensation of silanol groups between the bonding surfaces, reducing the atmospheric pressure to cause degassing from between the wafers, applying a compression force to the wafers with flat chucks so as to substantially eliminate the edge gap, and performing a permanent anneal bonding process.
摘要翻译： 包括晶片的氧化物 - 氧化物熔融粘合，其包括用具有至少平坦的中心区域和低于中心区域的外部环形区域的卡盘进行范德华力结合过程，安装的晶片的边缘部分朝向外部 环形区。 范德华合金波在外环形区域被破坏，导致边缘间隙。 进行热压接合工艺，其包括将结合的晶片加热到足以引发粘合表面之间的硅烷醇基团的缩合的温度，降低大气压力以引起晶片之间的脱气，用扁平卡盘向晶片施加压缩力 以便基本上消除边缘间隙，并进行永久退火接合工艺。
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46.发明申请THROUGH-SILICON VIA STRUCTURE AND METHOD FOR IMPROVING BEOL DIELECTRIC PERFORMANCE 审中-公开通过硅的结构和提高BEOL介电性能的方法公开(公告)号：US20150069608A1
公开(公告)日：2015-03-12
申请号：US14023980
申请日：2013-09-11
发明人： Christopher Collins , Troy Lawrence Graves-Abe , Mukta G. Farooq , Tze-man Ko , William Francis Landers , Youbo Lin , Son Van Nguyen , Jennifer Ann Oakley , Deepika Priyadarshini
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L23/5226 , H01L21/76831 , H01L21/76898 , H01L23/528 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An improved through-silicon via (TSV) and method of fabrication are disclosed. A back-end-of-line (BEOL) stack is formed on a semiconductor substrate. A TSV cavity is formed in the BEOL stack and semiconductor substrate. A conformal protective layer is disposed on the interior surface of the TSV cavity, along the BEOL stack and partway into the semiconductor substrate. The conformal protective layer serves to protect the dielectric layers within the BEOL stack during subsequent processing, improving the integrated circuit quality and product yield.
摘要翻译： 公开了一种改进的通硅通孔（TSV）和制造方法。 在半导体衬底上形成后端（BEOL）堆叠。 在BEOL堆叠和半导体衬底中形成TSV腔。 共形保护层沿着BEOL堆叠放置在TSV腔的内表面上，并且一部分设置在半导体衬底中。 共形保护层用于在后续处理期间保护BEOL堆叠内的电介质层，从而提高集成电路质量和产品产量。
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公开(公告)号：US20140353828A1
公开(公告)日：2014-12-04
申请号：US13905442
申请日：2013-05-30
发明人： Daniel C. Edelstein , Douglas C. La Tulipe, JR. , Wei Lin , Deepika Priyadarshini , Spyridon Skordas , Tuan A. Vo , Kevin R. Winstel
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L25/0657 , H01L21/76847 , H01L21/76849 , H01L21/76867 , H01L21/76885 , H01L21/76898 , H01L23/481 , H01L23/532 , H01L23/53233 , H01L23/5329 , H01L24/00 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/09 , H01L24/80 , H01L24/89 , H01L25/50 , H01L2224/03845 , H01L2224/05007 , H01L2224/0508 , H01L2224/05147 , H01L2224/05547 , H01L2224/05576 , H01L2224/05647 , H01L2224/05686 , H01L2224/08121 , H01L2224/08145 , H01L2224/08146 , H01L2224/80009 , H01L2224/80097 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2225/06513 , H01L2225/06541 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01026 , H01L2924/01027 , H01L2924/0104 , H01L2924/01041 , H01L2924/01042 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01322 , H01L2924/05442 , H01L2924/00014 , H01L2924/20111 , H01L2924/00
摘要： A metallic dopant element having a greater oxygen-affinity than copper is introduced into, and/or over, surface portions of copper-based metal pads and/or surfaces of a dielectric material layer embedding the copper-based metal pads in each of two substrates to be subsequently bonded. A dopant-metal silicate layer may be formed at the interface between the two substrates to contact portions of metal pads not in contact with a surface of another metal pad, thereby functioning as an oxygen barrier layer, and optionally as an adhesion material layer. A dopant metal rich portion may be formed in peripheral portions of the metal pads in contact with the dopant-metal silicate layer. A dopant-metal oxide portion may be formed in peripheral portions of the metal pads that are not in contact with a dopant-metal silicate layer.
摘要翻译： 将具有比铜更大的氧亲合力的金属掺杂剂元素引入到铜基金属焊盘和/或介电材料层的表面部分和/或其上的两个衬底中的铜基金属焊盘的表面上 随后保留。 可以在两个基板之间的界面处形成掺杂剂 - 金属硅酸盐层，以接触不与另一金属焊盘的表面接触的金属焊盘的部分，从而用作氧阻隔层，并且任选地作为粘合材料层。 可以在与掺杂剂 - 金属硅酸盐层接触的金属焊盘的周边部分中形成掺杂金属富集部分。 可以在不与掺杂剂 - 金属硅酸盐层接触的金属焊盘的周边部分中形成掺杂剂 - 金属氧化物部分。
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48.发明申请公开(公告)号：US20190148303A1
公开(公告)日：2019-05-16
申请号：US16224458
申请日：2018-12-18
发明人： Benjamin D. Briggs , Lawrence A. Clevenger , Chao-Kun Hu , Takeshi Nogami , Deepika Priyadarshini , Michael Rizzolo
IPC分类号： H01L23/538 , H01L21/768 , H01L23/532
CPC分类号： H01L23/5386 , H01L21/76846 , H01L21/76849 , H01L21/76858 , H01L21/76864 , H01L21/76867 , H01L21/76871 , H01L21/76879 , H01L21/76883 , H01L21/76886 , H01L23/53233 , H01L23/53238 , H01L23/5329
摘要： Low-temperature techniques for doping of Cu interconnects based on interfacially-assisted thermal diffusion are provided. In one aspect, a method of forming doped copper interconnects includes the steps of: patterning at least one trench in a dielectric material; forming a barrier layer lining the trench; forming a metal liner on the barrier layer; depositing a seed layer on the metal liner; plating a Cu fill into the trench to form Cu interconnects; removing a portion of a Cu overburden to access an interface between the metal liner and the Cu fill; depositing a dopant layer; and diffusing a dopant(s) from the dopant layer along the interface to form a Cu interconnect doping layer between the metal liner and the Cu fill. Alternatively, the overburden and the barrier layer/metal liner can be completely removed, and the dopant layer deposited selectively on the Cu fill. An interconnect structure is also provided.
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公开(公告)号：US10242933B2
公开(公告)日：2019-03-26
申请号：US15683316
申请日：2017-08-22
发明人： Griselda Bonilla , Elbert Huang , Son Nguyen , Takeshi Nogami , Christopher J. Penny , Deepika Priyadarshini
IPC分类号： H01L23/482 , H01L29/78 , H01L29/786 , H01L27/088 , H01L21/8234 , H01L29/423 , H01L29/49 , H01L29/66 , H01L21/768
摘要： Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.
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50.发明授权公开(公告)号：US10192829B2
公开(公告)日：2019-01-29
申请号：US15670387
申请日：2017-08-07
发明人： Benjamin D. Briggs , Lawrence A. Clevenger , Chao-Kun Hu , Takeshi Nogami , Deepika Priyadarshini , Michael Rizzolo
IPC分类号： H01L23/522 , H01L23/528 , H01L23/538 , H01L21/768 , H01L23/532
摘要： Low-temperature techniques for doping of Cu interconnects based on interfacially-assisted thermal diffusion are provided. In one aspect, a method of forming doped copper interconnects includes the steps of: patterning at least one trench in a dielectric material; forming a barrier layer lining the trench; forming a metal liner on the barrier layer; depositing a seed layer on the metal liner; plating a Cu fill into the trench to form Cu interconnects; removing a portion of a Cu overburden to access an interface between the metal liner and the Cu fill; depositing a dopant layer; and diffusing a dopant(s) from the dopant layer along the interface to form a Cu interconnect doping layer between the metal liner and the Cu fill. Alternatively, the overburden and the barrier layer/metal liner can be completely removed, and the dopant layer deposited selectively on the Cu fill. An interconnect structure is also provided.
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