公开(公告)号：US06348420B1

公开(公告)日：2002-02-19

申请号：US09471761

申请日：1999-12-23

Applicant: Ivo Raaijmakers ,  Chris Werkhoven

Inventor： Ivo Raaijmakers ,  Chris Werkhoven

IPC: H01L2131

CPC classification number: H01L21/28185 ,  C23C16/44 ,  H01L21/28017 ,  H01L21/28202 ,  H01L21/3144 ,  H01L21/3185 ,  H01L29/513 ,  H01L29/518

Abstract: Multiple sequential processes are conducted in situ in a single-wafer processing chamber, particularly for forming ultrathin dielectric stacks of high quality. The chamber exhibits single-pass, laminar gas flow, facilitating safe and clean sequential processing. Furthermore, a remote plasma source widens process windows, permitting isothermal sequential processing and thereby reducing the transition time for temperature ramping between in situ steps. In exemplary processes, extremely thin interfacial silicon oxide, nitride and/or oxynitride is grown, followed by in situ silicon nitride deposition. Cleaning, anneal and electrode deposition can also be conducted in situ, reducing transition time without commensurate loss in reaction rates.

Abstract translation: 在单晶片处理室中原位进行多次连续工艺，特别是用于形成高品质的超薄电介质叠层。 该室显示单程，层流气流，便于安全和清洁的顺序处理。 此外，远程等离子体源拓宽了工艺窗口，允许等温的顺序处理，从而减少了原位步骤之间温度斜坡的转换时间。 在示例性工艺中，生长极薄的界面氧化硅，氮化物和/或氮氧化物，随后进行原位氮化硅沉积。 清洗，退火和电极沉积也可以在原位进行，缩短过渡时间，而不会导致反应速率的相应损失。

公开(公告)号：US06183183B2

公开(公告)日：2001-02-06

申请号：US09006325

申请日：1998-01-13

Applicant: Dennis L. Goodwin ,  Eric R. Wood ,  Ivo Raaijmakers

Inventor： Dennis L. Goodwin ,  Eric R. Wood ,  Ivo Raaijmakers

IPC: B66C102

CPC classification number: H01L21/6838 ,  Y10S414/139 ,  Y10S414/141

Abstract: A dual-arm wafer hand-off assembly includes a pair of pickup arms for transferring wafers within a wafer processing system. The two pickup arms are adapted to move such that the wafer on one of the arms can be positioned over the other arm and handed off. In one version, a Bernoulli-style wand translates along a linear guideway and may be positioned over a paddle-style pickup arm. The wafer carried by the Bernoulli wand can be handed off to the paddle by shutting off the flow of gas from the Bernoulli wand jets. The two pickup arms may be mounted on linear slides and adapted to translate between a load/unload chamber and a processing chamber, or the guideway may be adapted to rotate to allow transfer of wafers to multiple processing chambers in a cluster system. One of the pickup arms is preferably an all-quartz Bernoulli-style pickup arm having a proximal arm portion and a distal wand. The arm portion is formed by a pair of juxtaposed plates with a gas passage therethrough, and the distal wand is also formed by a pair of juxtaposed plates with a plurality of gas passages therethrough. The arm portion and the wand are fused together at their junction region. A wafer stop element is formed by a single quartz rod and is clipped to the arm portion to present a plurality of wafer stop pegs at a proximal periphery of the wand. The wafer stop element may be rapidly installed or removed without fasteners or bonding.

Abstract translation: 双臂晶片切换组件包括一对用于在晶片处理系统内传送晶片的拾取臂。 两个拾取臂适于移动，使得其中一个臂上的晶片可以定位在另一个臂上方并被切掉。 在一个版本中，伯努利风格的魔杖沿着直线导轨转换，并且可以位于桨式拾音臂上。 伯努利魔杖携带的晶片可以通过关闭伯努利魔杖喷气机的气流来切换到桨叶。 两个拾取臂可以安装在线性滑块上并且适于在装载/卸载室和处理室之间平移，或者导轨可以适于旋转以允许将晶片传送到群集系统中的多个处理室。 拾取臂中的一个优选地是具有近端臂部分和远侧杖的全石英伯努利式拾取臂。 臂部由一对具有穿过其中的气体通道的并置的板形成，并且远端棒也由具有多个通过其的多个气体通道的一对并置的板形成。 手臂部分和魔杖在其连接区域融合在一起。 晶片止动元件由单个石英棒形成，并且被夹持到臂部分，以在棒的近端周边呈现多个晶片止动钉。 晶片止动元件可以在没有紧固件或粘合的情况下快速安装或移除。

公开(公告)号：US20110256718A1

公开(公告)日：2011-10-20

申请号：US13079562

申请日：2011-04-04

Applicant: Suvi P. Haukka ,  Ivo Raaijmakers ,  Wei Min Li ,  Juhana Kostamo ,  Hessel Sprey ,  Christiaan J. Werkhoven

Inventor： Suvi P. Haukka ,  Ivo Raaijmakers ,  Wei Min Li ,  Juhana Kostamo ,  Hessel Sprey ,  Christiaan J. Werkhoven

IPC: H01L21/285

CPC classification number: C23C16/029 ,  C23C16/34 ,  C23C16/401 ,  C23C16/403 ,  C23C16/405 ,  C23C16/452 ,  C23C16/45529 ,  C23C16/45531 ,  C23C16/45534 ,  C30B25/14 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28562 ,  H01L21/3141 ,  H01L21/3145 ,  H01L21/31612 ,  H01L21/3162 ,  H01L21/31641 ,  H01L21/3185 ,  H01L21/76846 ,  H01L21/76873 ,  H01L21/76879 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L2221/1089

Abstract: Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses can gradually increase in frequency, forming a transition region, until pure copper is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces. In some embodiments additional seed layers or additional transition layers are provided.

Abstract translation: 通过原子层沉积形成薄膜，由此膜的组成可以在包括自限制化学的交替脉冲的循环期间从单层变为单层。 在所示实施例中，在循环过程中引入了不同量的杂质源。 因此，即使对于非常薄的层也提供了梯度栅极电介质。 薄的2nm的栅极电介质可以从纯氧化硅到氧氮化物变化为氮化硅。 类似地，栅极电介质可以从氧化铝变化为氧化铝和较高电介质材料（例如，ZrO 2）到纯高k材料并返回到氧化铝的混合物。 在另一个实施例中，金属氮化物（例如，WN）首先形成为用于衬里双镶嵌沟槽和通孔的屏障。 在交替沉积工艺期间，铜可以被引入，例如分开的脉冲，并且铜源脉冲可以逐渐增加频率，形成过渡区域，直到在上表面形成纯铜。 有利的是，这些和各种其他情况下的分级组合物有助于避免诸如在尖锐材料界面处可能发生的蚀刻速率控制，电迁移和非欧姆电接触等问题。 在一些实施例中，提供了额外的种子层或附加的过渡层。

公开(公告)号：US07452757B2

公开(公告)日：2008-11-18

申请号：US10434423

申请日：2003-05-07

Applicant: Christiaan J. Werkhoven ,  Ivo Raaijmakers ,  Chantal Arena

Inventor： Christiaan J. Werkhoven ,  Ivo Raaijmakers ,  Chantal Arena

IPC: H01L21/00

CPC classification number: H01L21/31662 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/02356 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/3141 ,  H01L21/7624 ,  H01L21/76262

Abstract: Silicon-on-insulator (SOI) structures are provided by forming a single-crystal insulator over a substrate, followed by heteroepitaxy of a semiconductor layer thereover. Atomic layer deposition (ALD) is preferably used to form an amorphous insulator, followed by solid phase epitaxy to convert the layer into a single-crystal structure. Advantageously, the crystalline insulator has a lattice structure and lattice constant closely matching that of the semiconductor formed over it, and a ternary insulating material facilitates matching properties of the layers. Strained silicon can be formed without need for a buffer layer. An amorphous SiO2 layer can optionally be grown underneath the insulator. In addition, a buffer layer can be grown, either between the substrate and the insulator or between the insulator and the semiconductor layer, to produce desired strain in the active semiconductor layer.

Abstract translation: 通过在衬底上形成单晶绝缘体，然后在其上进行异质外延半导体层来提供绝缘体上硅（SOI）结构。 原子层沉积（ALD）优选用于形成非晶绝缘体，随后进行固相外延将层转化为单晶结构。 有利地，结晶绝缘体具有与其上形成的半导体的晶格结构和晶格常数紧密匹配的晶格绝缘体，并且三元绝缘材料有助于层的匹配性质。 可以形成应变硅，而不需要缓冲层。 可以任选地在绝缘体下方生长非晶SiO 2层。 此外，可以在衬底和绝缘体之间或绝缘体和半导体层之间生长缓冲层，以在有源半导体层中产生期望的应变。

公开(公告)号：US07323422B2

公开(公告)日：2008-01-29

申请号：US10379516

申请日：2003-03-04

Applicant: Ivo Raaijmakers ,  Pekka J. Soininen ,  Jan Willem Maes

Inventor： Ivo Raaijmakers ,  Pekka J. Soininen ,  Jan Willem Maes

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L28/56 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: High dielectric constant (high-k) materials are formed directly over oxidation-susceptible conductors such as silicon. A discontinuous layer is formed, with gaps between grains of the high-k material. Exposed conductor underneath the grain boundaries is oxidized or nitridized to form, e.g., silicon dioxide or silicon nitride, when exposed to oxygen or nitrogen source gases at elevated temperatures. This dielectric growth is preferential underneath the grain boundaries such that any oxidation or nitridation at the interface between the high-k material grains and covered conductor is not as extensive. The overall dielectric constant of the composite film is high, while leakage current paths between grains is reduced. Ultrathin high-k materials with low leakage current are thereby enabled.

Abstract translation: 高介电常数（高k）材料直接在氧化敏感导体（如硅）上形成。 形成不连续层，在高k材料的晶粒之间形成间隙。 在高温下暴露于氧或氮源气体时，在晶界之下的暴露导体被氧化或氮化以形成例如二氧化硅或氮化硅。 这种电介质生长优选在晶界之下，使得在高k材料晶粒和被覆导体之间的界面处的任何氧化或氮化不是很广泛。 复合膜的总介电常数高，而晶粒间的漏电流路径减小。 从而能够实现低泄漏电流的超薄高k材料。

公开(公告)号：US20080003763A1

公开(公告)日：2008-01-03

申请号：US11853400

申请日：2007-09-11

Applicant: Ivo Raaijmakers ,  Christophe Pomarede ,  Cornelius Jeugd ,  Alexander Gschwandtner ,  Andreas Grassi

Inventor： Ivo Raaijmakers ,  Christophe Pomarede ,  Cornelius Jeugd ,  Alexander Gschwandtner ,  Andreas Grassi

IPC: H01L21/334

CPC classification number: C23C16/45504 ,  C23C16/045 ,  C23C16/24 ,  C23C16/455 ,  C23C16/45502 ,  C23C16/45591 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/28525 ,  H01L21/28556 ,  H01L21/76877 ,  H01L29/66181 ,  H01L29/78

Abstract: A method is disclosed for depositing silicon with high deposition rates and good step coverage. The process is performed at high pressures, including close to atmospheric pressures, at temperatures of greater than about 650° C. Silane and hydrogen are flowed over a substrate in a single-wafer chamber. Advantageously, the process maintains good step coverage and high deposition rates (e.g., greater that 50 nn/min) even when dopant gases are added to the process, resulting in commercially practicable rates of deposition for conductive silicon. Despite the high deposition rates, step coverage is sufficient to deposit polysilicon into extremely deep trenches and vias with aspect ratios as high as 40:1, filling such structures without forming voids or keyholes.

Abstract translation: 公开了一种用于沉积具有高沉积速率和良好的台阶覆盖率的硅的方法。 该方法在大于约650℃的温度下在高压（包括接近大气压）下进行。硅烷和氢气在单晶片室中流过衬底。 有利的是，即使将掺杂剂气体加入到该方法中，该方法保持良好的阶梯覆盖率和高的沉积速率（例如，大于50nn / min），从而导致商业上可行的导电硅沉积速率。 尽管沉积速率高，但步长覆盖足以将多晶硅沉积到具有高达40:1的纵横比的极深沟槽和通孔中，填充这种结构而不形成空隙或键孔。

公开(公告)号：US07238595B2

公开(公告)日：2007-07-03

申请号：US10800390

申请日：2004-03-12

Applicant: Paul D. Brabant ,  Joseph P. Italiano ,  Chantal J. Arena ,  Pierre Tomasini ,  Ivo Raaijmakers ,  Matthias Bauer

Inventor： Paul D. Brabant ,  Joseph P. Italiano ,  Chantal J. Arena ,  Pierre Tomasini ,  Ivo Raaijmakers ,  Matthias Bauer

IPC: H01L21/20

CPC classification number: C30B25/02 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02661

Abstract: Methods for depositing epitaxial films such as epitaxial Ge and SiGe films. During cooling from high temperature processing to lower deposition temperatures for Ge-containing layers, Si or Ge compounds are provided to the substrate. Smooth, thin, relatively defect-free Ge or SiGe layers result. Retrograded relaxed SiGe is also provided between a relaxed, high Ge-content seed layer and an overlying strained layer.

Abstract translation: 用于沉积诸如外延Ge和SiGe膜的外延膜的方法。 在从高温加工冷却到含Ge层的较低沉积温度时，向基板提供Si或Ge化合物。 导致平滑，薄，相对缺陷的Ge或SiGe层。 还提供了轻松，高Ge含量种子层和上覆应变层之间的退化弛豫SiGe。

公开(公告)号：US20060281322A1

公开(公告)日：2006-12-14

申请号：US11506320

申请日：2006-08-18

Applicant: Paul Brabant ,  Joseph Italiano ,  Chantal Arena ,  Pierre Tomasini ,  Ivo Raaijmakers ,  Matthias Bauer

Inventor： Paul Brabant ,  Joseph Italiano ,  Chantal Arena ,  Pierre Tomasini ,  Ivo Raaijmakers ,  Matthias Bauer

IPC: H01L21/461

CPC classification number: C30B25/02 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02661

Abstract: Methods for depositing epitaxial films such as epitaxial Ge and SiGe films. During cooling from high temperature processing to lower deposition temperatures for Ge-containing layers, Si or Ge compounds are provided to the substrate. Smooth, thin, relatively defect-free Ge or SiGe layers result. Retrograded relaxed SiGe is also provided between a relaxed, high Ge-content seed layer and an overlying strained layer.

公开(公告)号：US07112538B2

公开(公告)日：2006-09-26

申请号：US10293795

申请日：2002-11-12

Applicant: Armand Ferro ,  Ivo Raaijmakers ,  Derrick Foster

Inventor： Armand Ferro ,  Ivo Raaijmakers ,  Derrick Foster

IPC: H01L21/31

CPC classification number: C30B29/06 ,  C23C16/4405 ,  C23C16/481 ,  C30B25/02 ,  C30B25/105 ,  C30B25/14 ,  C30B33/005 ,  C30B33/02 ,  C30B33/12 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02301 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02661 ,  H01L21/28017 ,  H01L21/31116 ,  H01L21/31612 ,  H01L21/31662 ,  H01L29/66651

Abstract: A single-wafer, chemical vapor deposition reactor is provided with hydrogen and silicon source gas suitable for epitaxial silicon deposition, as well as a safe mixture of oxygen in a non-reactive gas. Methods are provided for forming oxide and silicon layers within the same chamber. In particular, a sacrificial oxidation is performed, followed by a hydrogen bake to sublime the oxide and leave a clean substrate. Epitaxial deposition can follow in situ. A protective oxide can also be formed over the epitaxial layer within the same chamber, preventing contamination of the critical epitaxial layer. Alternatively, the oxide layer can serve as the gate dielectric, and a polysilicon gate layer can be formed in situ over the oxide.

公开(公告)号：US07060132B2

公开(公告)日：2006-06-13

申请号：US10270745

申请日：2002-10-11

Applicant: Sven Lindfors ,  Ivo Raaijmakers

Inventor： Sven Lindfors ,  Ivo Raaijmakers

IPC: C30B23/00

CPC classification number: C30B25/14 ,  C23C16/45502 ,  C23C16/45546 ,  C23C16/4583 ,  C30B25/02 ,  C30B25/08

Abstract: A method and apparatus for growing a thin film onto a substrate is disclosed. According to one embodiment, a plurality of substrates, each having a width and a length, are placed in a reaction space and the substrates are subjected to surface reactions of vapor-phase reactants according to the ALD method to form a thin film on the surfaces of the substrates. The reaction space comprises an elongated gas channel having a cross-section with a width greater that the height and which has a length which is at least 2 times greater than the length of one substrate in the direction of the gas flow in the channel, the channel having a folded configuration with at least one approximately 180 degree turn in the direction of the gas flow.