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41.发明授权公开(公告)号：US10096713B1
公开(公告)日：2018-10-09
申请号：US15619923
申请日：2017-06-12
发明人： Dechao Guo , Hemanth Jagannathan , Shogo Mochizuki , Gen Tsutsui , Chun-Chen Yeh
IPC分类号： H01L29/78 , H01L29/08 , H01L29/165 , H01L29/66 , H01L21/02 , H01L21/306 , H01L21/3065
摘要： After forming a gate structure over a semiconductor fin that extends upwards from a semiconductor substrate portion, a sigma cavity is formed within the semiconductor fin on each side of the gate structure. A semiconductor buffer region composed of an un-doped stress-generating semiconductor material is epitaxially growing from faceted surfaces of the sigma cavity. Finally, a doped semiconductor region composed of a doped stress-generating semiconductor material is formed on the semiconductor buffer region to completely fill the sigma cavity. The doped semiconductor region is formed to have substantially vertical sidewalls for formation of a uniform source/drain junction profile.
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公开(公告)号：US20180269274A1
公开(公告)日：2018-09-20
申请号：US15805829
申请日：2017-11-07
发明人： Kisup Chung , Isabel C. Estrada-Raygoza , Hemanth Jagannathan , Chi-Chun Liu , Yann A.M. Mignot , Hao Tang
IPC分类号： H01L49/02
CPC分类号： H01L28/60
摘要： Methods of forming capacitors include forming a self-assembled pattern of periodic first and second domains using first and second block copolymer materials over a substrate. The second block copolymer material is etched away. Material from the substrate is etched based on a pattern defined by the first block copolymer material to form cavities in the substrate. A capacitor stack is conformally deposited over the substrate, such that the capacitor stack is formed on horizontal surfaces of the substrate and vertical surfaces of the cavities.
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43.发明申请公开(公告)号：US20180211885A1
公开(公告)日：2018-07-26
申请号：US15412499
申请日：2017-01-23
IPC分类号： H01L21/8238 , H01L27/092 , H01L21/311
CPC分类号： H01L21/823857 , H01L21/823807 , H01L27/092
摘要： A method is presented for forming a semiconductor structure. The method includes forming a silicon (Si) channel for a first device, forming a first interfacial layer over the Si channel, forming a silicon-germanium (SiGe) channel for a second device, forming a second interfacial layer over the SiGe channel, and selectively removing germanium oxide (GeOX) from the second interfacial layer by applying a combination of hydrogen (H2) and hydrogen chloride (HCl). The second interfacial is silicon germanium oxide (SiGeOX) and removal of the GeOX results in formation of a pure silicon dioxide (SiO2) layer.
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44.发明授权公开(公告)号：US10002791B1
公开(公告)日：2018-06-19
申请号：US15481012
申请日：2017-04-06
IPC分类号： H01L21/28 , H01L21/8234 , H01L27/088 , H01L27/092 , H01L21/8238 , H01L29/49 , H01L29/66
CPC分类号： H01L21/82345 , H01L21/823487 , H01L21/823821 , H01L21/823842 , H01L21/823885 , H01L27/088 , H01L27/092 , H01L27/0924 , H01L29/4958 , H01L29/4966 , H01L29/66545 , H01L29/785
摘要： A method is presented for forming a device having multiple field effect transistors (FETs) with each FET having a different work function. In particular, the method includes forming multiple microchips in which each FET has a different threshold voltage (Vt) or work-function. In one embodiment, four FETs are formed over a semiconductor substrate. Each FET has a source, drain and a gate electrode. Each gate electrode is processed independently to provide a substantially different threshold voltage.
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公开(公告)号：US09978748B2
公开(公告)日：2018-05-22
申请号：US14964445
申请日：2015-12-09
IPC分类号： H01L27/088 , H01L29/66 , H01L21/311 , H01L21/02
CPC分类号： H01L27/0886 , H01L21/02532 , H01L21/31122 , H01L21/31144 , H01L21/823431 , H01L21/823481 , H01L29/66545 , H01L29/6656 , H01L29/66795 , H01L29/785
摘要： A method is provided for forming an integrated circuit with FinFETs. Initially, a fin is received with a dummy gate passing thereover. The dummy gate is removed to form a space over the fin. A temporary layer is subsequently placed in the space, and an element from the temporary layer is caused to pass into a portion of the fin to form a modified fin portion. After the temporary layer is removed, at least part of the modified fin portion is etched away to form a gap in the fin.
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公开(公告)号：US20180076040A1
公开(公告)日：2018-03-15
申请号：US15262206
申请日：2016-09-12
IPC分类号： H01L21/28 , H01L21/02 , H01L29/66 , H01L29/161 , H01L29/51
CPC分类号： H01L21/28255 , H01L21/0214 , H01L21/02164 , H01L21/02236 , H01L21/02247 , H01L21/02255 , H01L29/161 , H01L29/513 , H01L29/66545 , H01L29/78 , H01L29/785
摘要： Methods are provided to form pure silicon oxide layers on silicon-germanium (SiGe) layers, as well as an FET device having a pure silicon oxide interfacial layer of a metal gate structure formed on a SiGe channel layer of the FET device. For example, a method comprises growing a first silicon oxide layer on a surface of a SiGe layer using a first oxynitridation process, wherein the first silicon oxide layer comprises nitrogen. The first silicon oxide layer is removed, and a second silicon oxide layer is grown on the surface of the SiGe layer using a second oxynitridation process, which is substantially the same as the first oxynitridation process, wherein the second silicon oxide layer is substantially devoid of germanium oxide and nitrogen. For example, the first silicon oxide layer comprises a SiON layer and the second silicon oxide layer comprises a pure silicon dioxide layer.
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公开(公告)号：US20170278939A1
公开(公告)日：2017-09-28
申请号：US15620253
申请日：2017-06-12
IPC分类号： H01L29/45 , H01L29/08 , H01L21/8234 , H01L21/768 , H01L27/088
CPC分类号： H01L29/45 , H01L21/76802 , H01L21/76846 , H01L21/76847 , H01L21/7685 , H01L21/76858 , H01L21/76882 , H01L21/76897 , H01L21/823418 , H01L21/823425 , H01L21/823431 , H01L21/823475 , H01L23/485 , H01L23/5226 , H01L23/53238 , H01L23/53266 , H01L27/0886 , H01L29/0847 , H01L29/41791 , H01L29/456 , H01L29/665 , H01L29/66628 , H01L29/78
摘要： Source/drain contact structures that exhibit low contact resistance and improved electromigration properties are provided. After forming a first contact conductor portion comprising a metal having a high resistance to electromigration such as tungsten at a bottom portion of source/drain contact trench to form direct contact with a source/drain region of a field effect transistor, a second contact conductor portion comprising a highly conductive metal such as copper or a copper alloy is formed over the first contact conductor portion.
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公开(公告)号：US09761655B1
公开(公告)日：2017-09-12
申请号：US15186919
申请日：2016-06-20
IPC分类号： H01L49/02 , H01L21/20 , H01L29/06 , H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L28/75 , H01L21/76879 , H01L21/76883 , H01L23/5226 , H01L23/53257 , H01L29/0649
摘要： Stacked planar capacitor structures and methods of fabricating the same generally include stacking two or more capacitors with three electrodes by sharing a middle electrode, wherein each capacitor has a different area. The stacked structure does not include step heights, which permits fabrication of multiple structures where desired.
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公开(公告)号：US20170229459A1
公开(公告)日：2017-08-10
申请号：US15284759
申请日：2016-10-04
IPC分类号： H01L27/092 , H01L29/267 , H01L29/165 , H01L29/78 , H01L29/10 , H01L21/8238 , H01L21/02 , H01L29/20 , H01L29/08
CPC分类号： H01L27/0921 , H01L21/0245 , H01L21/02532 , H01L21/02538 , H01L21/02546 , H01L21/0262 , H01L21/302 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823892 , H01L21/8252 , H01L21/8258 , H01L27/0605 , H01L27/0924 , H01L29/0847 , H01L29/1083 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/20 , H01L29/267 , H01L29/66545 , H01L29/7848
摘要： A method for forming a semiconductor device comprises forming an insulator layer on a semiconductor substrate, removing portions of the insulator layer to form a first cavity and a second cavity, the first cavity exposing a first portion of the semiconductor substrate an the second cavity exposing a second portion of the semiconductor substrate, growing a first semiconductor material in the first cavity and the second cavity. Growing a second semiconductor material on the first semiconductor material in the first cavity and the second cavity, growing a third semiconductor material on the second semiconductor material in the first cavity and the second cavity. Forming a mask over the third semiconductor material in the first cavity, removing the third semiconductor material from the second cavity to expose the second semiconductor material in the second cavity, and growing a fourth semiconductor material on the second semiconductor material in the second cavity.
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50.发明授权公开(公告)号：US09721842B2
公开(公告)日：2017-08-01
申请号：US15058309
申请日：2016-03-02
发明人： Takashi Ando , Hemanth Jagannathan , Balaji Kannan , Siddarth A. Krishnan , Unoh Kwon , Rekha Rajaram
IPC分类号： H01L21/76 , H01L21/8234 , H01L21/3213 , H01L21/28 , H01L21/321 , H01L21/033 , H01L21/225 , H01L21/311 , H01L21/3115 , H01L21/324 , H01L29/66 , H01L29/49 , H01L21/8238 , H01L21/027 , H01L21/02 , H01L29/51
CPC分类号： H01L21/823462 , H01L21/02321 , H01L21/0273 , H01L21/0332 , H01L21/225 , H01L21/28079 , H01L21/28088 , H01L21/28185 , H01L21/28194 , H01L21/28229 , H01L21/31111 , H01L21/31116 , H01L21/31144 , H01L21/3115 , H01L21/32115 , H01L21/32133 , H01L21/32134 , H01L21/32135 , H01L21/32139 , H01L21/324 , H01L21/823437 , H01L21/82345 , H01L21/823842 , H01L21/823857 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： A method of fabricating advanced node field effect transistors using a replacement metal gate process. The method includes dopant a high-k dielectric directly or indirectly by using layers composed of multi-layer thin film stacks, or in other embodiments, by a single blocking layer. By taking advantage of unexpected etch selectivity of the multi-layer stack or the controlled etch process of a single layer stack, etch damage to the high-k may be avoided and work function metal thicknesses can be tightly controlled which in turn allows field effect transistors with low Tinv (inverse of gate capacitance) mismatch.
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