公开(公告)号：US20100230803A1

公开(公告)日：2010-09-16

申请号：US12722486

申请日：2010-03-11

申请人： Wen-Cheng CHIEN ,  Ching-Yu Ni ,  Shu-Ming Chang

发明人： Wen-Cheng CHIEN ,  Ching-Yu Ni ,  Shu-Ming Chang

IPC分类号： H01L23/48 ,  H01L21/60 ,  H01L23/488

CPC分类号： B05D1/36 ,  B81B2207/096 ,  B81C1/00301 ,  H01L21/56 ,  H01L21/6835 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L27/14618 ,  H01L31/02002 ,  H01L31/0203 ,  H01L33/486 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01078 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/00

摘要： An embodiment of the invention provides a method for forming an electronic device package, which includes providing a carrier substrate having an upper surface and an opposite lower surface; forming a cavity from the upper surface of the carrier substrate; disposing an electronic device having a conducting electrode in the cavity; forming a filling layer in the cavity, wherein the filling layer surround the electronic device; thinning the carrier substrate from the lower surface to a predetermined thickness; forming at least a through-hole in the electronic device or the in the carrier substrate; and forming a conducting layer over a sidewall of the through-hole, wherein the conducting layer electrically connects to the conducting electrode.

摘要翻译： 本发明的实施例提供了一种形成电子器件封装的方法，该方法包括提供具有上表面和相对下表面的载体衬底; 从所述载体基板的上表面形成空腔; 将具有导电电极的电子设备设置在空腔中; 在所述空腔中形成填充层，其中所述填充层围绕所述电子设备; 将载体基板从下表面变薄到预定厚度; 在电子设备或载体衬底中形成至少一个通孔; 以及在所述通孔的侧壁上形成导电层，其中所述导电层与所述导电电极电连接。

公开(公告)号：US07772679B2

公开(公告)日：2010-08-10

申请号：US12213660

申请日：2008-06-23

申请人： Shu-Ming Chang ,  Ying-Ching Shih

发明人： Shu-Ming Chang ,  Ying-Ching Shih

IPC分类号： H01L21/00

CPC分类号： H01L23/552 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/3025 ,  H01L2224/05599 ,  H01L2224/05099

摘要： This invention provides a magnetic shielding package structure of a magnetic memory device, in which at least a magnetic memory device is embedded between a magnetic shielding substrate and a magnetic shielding layer. A plurality of through vias is formed in the magnetic shielding substrate or the magnetic shielding layer, and a plurality of conductive contacts passes through the through vias such that electrical connection between the magnetic memory device and the external is established.

摘要翻译： 本发明提供一种磁存储器件的磁屏蔽封装结构，其中至少一个磁存储器件被嵌入在磁屏蔽衬底和磁屏蔽层之间。 在磁屏蔽基板或磁屏蔽层中形成多个通孔，并且多个导电触头通过通孔，从而建立磁存储器件与外部之间的电连接。

公开(公告)号：US20100052099A1

公开(公告)日：2010-03-04

申请号：US12364543

申请日：2009-02-03

申请人： Shu-Ming Chang ,  Chia-Wen Chiang

发明人： Shu-Ming Chang ,  Chia-Wen Chiang

IPC分类号： H01L29/92 ,  H01L21/20

CPC分类号： H01L23/642 ,  H01L23/481 ,  H01L23/50 ,  H01L25/0657 ,  H01L28/91 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05599

摘要： This invention provides a capacitor device with a high dielectric constant material and multiple vertical electrode plates. The capacitor devices can be directly fabricated on a wafer with low temperature processes so as to be integrated with active devices formed on the wafer. This invention also forms vertical conducting lines in the capacitor devices using the through-silicon-via technology to facilitate the three-dimensional stacking of the capacitor devices.

摘要翻译： 本发明提供具有高介电常数材料和多个垂直电极板的电容器装置。 电容器器件可以直接制造在具有低温工艺的晶片上，以便与形成在晶片上的有源器件集成。 本发明还在电容器器件中使用穿硅通孔技术形成垂直导线，以促进电容器器件的三维堆叠。

公开(公告)号：US20100032830A1

公开(公告)日：2010-02-11

申请号：US12500780

申请日：2009-07-10

申请人： Hsiang-Hung Chang ,  Shu-Ming Chang ,  Tzu-Ying Kuo ,  Yuan-Chang Lee

发明人： Hsiang-Hung Chang ,  Shu-Ming Chang ,  Tzu-Ying Kuo ,  Yuan-Chang Lee

IPC分类号： H01L23/498 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L27/14618 ,  H01L27/14643 ,  H01L27/14683 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/12105 ,  H01L2224/24226 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/00

摘要： The three-dimensional conducting structure comprises a substrate, a first redistributed conductor, a second redistributed conductor and an insulator. The substrate has an active surface, a passive surface opposite to the active one, a pad on the active surface and a through hole. The first redistributed conductor comprises a projecting portion and a receiving portion. The projecting portion is projected from the active surface and electrically connected to the pad. The receiving portion is outside the active surface and in contact with the projecting portion, both of which constitute a recess communicating with the through hole. The second redistributed conductor is positioned within the through hole and the recess, in contact with the receiving portion, and extended toward the passive surface along the through hole. The insulator is filled between the second redistributed conductor and the substrate and between the second redistributed conductor and the projecting portion.

摘要翻译： 三维导电结构包括衬底，第一再分布导体，第二再分布导体和绝缘体。 衬底具有活性表面，与活性表面相对的无源表面，活性表面上的焊盘和通孔。 第一再分布导体包括突出部分和接收部分。 突出部分从有源表面突出并电连接到焊盘。 接收部分在活性表面之外并且与突出部分接触，两者都构成与通孔连通的凹部。 第二再分布导体定位在通孔内，凹部与接收部分接触，并沿着通孔向被动表面延伸。 绝缘体填充在第二再分布导体和衬底之间以及第二再分布导体和突出部分之间。

公开(公告)号：US20090267536A1

公开(公告)日：2009-10-29

申请号：US12232125

申请日：2008-09-11

申请人： Chen-Hsung Wang ,  Shu-Ming Chang

发明人： Chen-Hsung Wang ,  Shu-Ming Chang

IPC分类号： H05B41/36

CPC分类号： H05B41/2855

摘要： A fluorescent lamp driver circuit is provided. The fluorescent lamp driver circuit uses reversed current detecting signal to achieve feedback control and circuit protection so as to simplify the driver circuit and reduces the number of the required electronic components. The driver circuit needs a single control unit to control the whole circuit, which not only reduces cost, but also simplifies circuit design.

摘要翻译： 提供荧光灯驱动电路。 荧光灯驱动电路使用反向电流检测信号来实现反馈控制和电路保护，以简化驱动电路并减少所需电子部件的数量。 驱动电路需要一个控制单元来控制整个电路，不仅可以降低成本，而且简化电路设计。

公开(公告)号：US20080308928A1

公开(公告)日：2008-12-18

申请号：US12010617

申请日：2008-01-28

申请人： Shu-Ming Chang ,  Tzu-Ying Kuo ,  Chia-Wen Chiang ,  Hsiang-Hung Chang

发明人： Shu-Ming Chang ,  Tzu-Ying Kuo ,  Chia-Wen Chiang ,  Hsiang-Hung Chang

IPC分类号： H01L23/34

CPC分类号： H01L27/14618 ,  H01L24/19 ,  H01L24/24 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/16 ,  H01L27/14634 ,  H01L2223/6677 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/051 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/12105 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05599

摘要： This invention provides an image sensor module with a three-dimensional die-stacking structure. By filling a conductive material into through silicon vias within at least one image sensor die, and into via holes within an insulating layer, vertical electrical connections are formed between the image sensor die and an image processor buried in the insulating layer. A plurality of solder bumps is formed on a backside of the image sensor module so that the module can be directly assembled onto a circuit board. The image sensor module of this invention is characterized by a wafer-level packaging architecture and a three-dimensional die-stacking structure, which reduces electrical connection lengths within the module and thus reduces an area and height of the whole packaged module.

摘要翻译： 本发明提供一种具有三维管芯堆叠结构的图像传感器模块。 通过将导电材料填充到至少一个图像传感器芯片内的通孔硅中，并且在绝缘层内的通孔中，在图像传感器裸片和埋在绝缘层中的图像处理器之间形成垂直电连接。 多个焊料凸块形成在图像传感器模块的背面，使得模块可以直接组装到电路板上。 本发明的图像传感器模块的特征在于晶片级封装结构和三维管芯堆叠结构，其减小了模块内的电连接长度，从而减小了整个封装模块的面积和高度。

公开(公告)号：US20080014679A1

公开(公告)日：2008-01-17

申请号：US11589122

申请日：2006-10-30

申请人： Lee-Cheng Shen ,  Shu-Ming Chang

发明人： Lee-Cheng Shen ,  Shu-Ming Chang

IPC分类号： H01L21/00

CPC分类号： H01L24/96 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/562 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A packaging structure with protective layers and a packaging method thereof are provided. A protective layer is formed on the surface and the pre-dicing line of the wafer to protect the chip and the die during the wafer grinding process, so as to prevent the wafer from being damaged due to the collision during the transportation process, and thereby reinforcing the mechanical strength of the wafer and the chip, which is useful for the subsequent packaging process.

摘要翻译： 提供具有保护层的包装结构及其包装方法。 在晶片研磨过程中，在晶片的表面和预切割线上形成保护层以保护芯片和晶粒，从而防止晶片在运输过程中由于碰撞而被损坏，从而 增强晶片和芯片的机械强度，这对于随后的包装过程是有用的。

公开(公告)号：US20070157186A1

公开(公告)日：2007-07-05

申请号：US11407940

申请日：2006-04-21

申请人： Fu-Chiung Cheng ,  Shu-Ming Chang ,  Jian-Yi Chen ,  Kuan-Yu Yan ,  Shin-Hway Yu ,  Chin-Tai Chou

发明人： Fu-Chiung Cheng ,  Shu-Ming Chang ,  Jian-Yi Chen ,  Kuan-Yu Yan ,  Shin-Hway Yu ,  Chin-Tai Chou

IPC分类号： G06F9/45 ,  G06F9/44

CPC分类号： G06F17/5045

摘要： A method to hardware component graph translation process for a high-level programming language, which analyzes codes of a high-level programming language to collect class information and store the collected class information in a class information object, and generates a temporal hardware component graph to obtain corresponding public methods, parameters, return values. The public methods, parameters, return values are linked to a class start node. A method call table is generated according to both one or more in/out edges of a method call node and method information of the class information object. The one or more edges linked to the method call node are changed to a method start node according to the method call table to accordingly represent a respective method call in the codes of the high-level programming language and translate the temporal hardware component graph into a hardware component graph allowable to correspond to hardware components.

摘要翻译： 一种用于高级编程语言的硬件组件图形转换过程的方法，其分析高级编程语言的代码以收集类信息并将收集的类信息存储在类信息对象中，并且生成时间硬件组件图 获取相应的公共方法，参数，返回值。 公共方法，参数，返回值链接到类起始节点。 根据方法调用节点的一个或多个进/出边和类信息对象的方法信息生成方法调用表。 链接到方法调用节点的一个或多个边缘根据方法调用表被改变为方法开始节点，以相应地表示高级编程语言的代码中的相应方法调用，并将时间硬件组件图形转换为 硬件组件图可以对应于硬件组件。

公开(公告)号：US08710680B2

公开(公告)日：2014-04-29

申请号：US13052769

申请日：2011-03-21

申请人： Shu-Ming Chang ,  Bai-Yao Lou ,  Ying-Nan Wen ,  Chien-Hung Liu

发明人： Shu-Ming Chang ,  Bai-Yao Lou ,  Ying-Nan Wen ,  Chien-Hung Liu

IPC分类号： H01L29/40

CPC分类号： H01L21/50 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/81 ,  H01L24/92 ,  H01L24/93 ,  H01L24/94 ,  H01L33/62 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/03825 ,  H01L2224/039 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/056 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11825 ,  H01L2224/119 ,  H01L2224/1191 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/136 ,  H01L2224/16225 ,  H01L2224/32052 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/92142 ,  H01L2224/92143 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2224/0231 ,  H01L2224/11 ,  H01L2224/1182 ,  H01L2224/03 ,  H01L2224/0382 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05552

摘要： An electronic device package is disclosed. The package includes at least one semiconductor chip having a first surface and a second surface opposite thereto, in which at least one redistribution layer is disposed on the first surface of the semiconductor chip and is electrically connected to at least one conductive pad structure. At least one abut portion is disposed on the redistribution layer and electrically contacting thereto. A passivation layer covers the first surface of the semiconductor chip and surrounds the abut portion. A substrate is attached onto the second surface of the semiconductor chip. A fabrication method of the electronic device package is also disclosed.

摘要翻译： 公开了一种电子器件封装。 该封装包括至少一个具有第一表面和与其相对的第二表面的半导体芯片，其中至少一个再分配层设置在半导体芯片的第一表面上并与至少一个导电焊盘结构电连接。 至少一个邻接部分设置在再分布层上并与其电接触。 钝化层覆盖半导体芯片的第一表面并围绕邻接部分。 将衬底附着到半导体芯片的第二表面上。 还公开了一种电子器件封装的制造方法。

公开(公告)号：US08633582B2

公开(公告)日：2014-01-21

申请号：US12702482

申请日：2010-02-09

申请人： Shu-Ming Chang ,  Cheng-Te Chou

发明人： Shu-Ming Chang ,  Cheng-Te Chou

IPC分类号： H01L23/48

CPC分类号： H01L23/5389 ,  H01L23/16 ,  H01L23/3121 ,  H01L23/49816 ,  H01L24/19 ,  H01L24/28 ,  H01L24/83 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83101 ,  H01L2224/83136 ,  H01L2224/83855 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/03

摘要： A chip package is disclosed. The package includes a carrier substrate and at least one semiconductor chip thereon. The semiconductor chip has a plurality of conductive pads, where a plurality of first redistribution layers (RDLs) is disposed thereon and is electrically connected thereto. A single-layer insulating structure covers the carrier substrate and the semiconductor chip, having a plurality of openings exposing the plurality of first RDLs. A plurality of second RDLs is disposed on the single-layer insulating structure and is electrically connected to the plurality of first RDLs. A passivation layer is disposed on the single-layer insulating structure and the plurality of second RDLs, having a plurality of openings exposing the plurality of second RDLs. A plurality of conductive bumps is correspondingly disposed in the plurality of openings to be electrically connected to the plurality of second RDLs. A fabrication method of the chip package is also disclosed.

摘要翻译： 公开了一种芯片封装。 该封装包括载体基板和其上的至少一个半导体芯片。 半导体芯片具有多个导电焊盘，其中多个第一再分配层（RDL）设置在其上并与其电连接。 单层绝缘结构覆盖载体基板和具有暴露多个第一RDL的多个开口的半导体芯片。 多个第二RDL设置在单层绝缘结构上并且电连接到多个第一RDL。 钝化层设置在单层绝缘结构上，并且多个第二RDL具有暴露多个第二RDL的多个开口。 多个导电凸块相应地设置在多个开口中以电连接到多个第二RDL。 还公开了芯片封装的制造方法。