公开(公告)号：US20170077017A1

公开(公告)日：2017-03-16

申请号：US15361700

申请日：2016-11-28

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49575 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/00 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/072 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/3716 ,  H01L2224/37599 ,  H01L2224/40245 ,  H01L2224/45015 ,  H01L2224/48106 ,  H01L2224/48108 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49173 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1425 ,  H01L2924/1426 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H02M3/155 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/20752 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2224/05599

Abstract: Disclosed embodiments relate to a semiconductor device. A semiconductor device is fabricated by attachment of a first chip to a first surface of a pad of a leadframe. Each of one or more terminals of the first chip is connected to a respective lead of the leadframe. The first chip and the first surface of the pad are then encapsulated in a packaging material, while leaving an opposite second surface of the pad exposed. A second chip is attached to a recessed portion of the second surface of the pad so that at least one terminal of the second chip is substantially coplanar with an un-recessed portion of the second surface. In one embodiment, a third chip is also attached to the recessed portion of the second surface so that at least one terminal of the third chip is substantially coplanar with the un-recessed portion of the second surface.

Abstract translation: 公开的实施例涉及半导体器件。 通过将第一芯片附接到引线框的焊盘的第一表面来制造半导体器件。 第一芯片的一个或多个端子中的每一个连接到引线框架的相应引线。 然后将第一芯片和垫的第一表面封装在包装材料中，同时使衬垫的相对的第二表面露出。 第二芯片附接到焊盘的第二表面的凹陷部分，使得第二芯片的至少一个端子与第二表面的未凹陷部分基本上共面。 在一个实施例中，第三芯片也附接到第二表面的凹部，使得第三芯片的至少一个端子与第二表面的未凹陷部分基本共面。

公开(公告)号：US09543240B2

公开(公告)日：2017-01-10

申请号：US15090176

申请日：2016-04-04

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil

IPC: H01L23/495 ,  H01L25/16 ,  H01L25/00 ,  H01L23/00 ,  H01L25/07 ,  H02M3/155 ,  H01L23/31

CPC classification number: H01L23/49575 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/072 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/3716 ,  H01L2224/37599 ,  H01L2224/40245 ,  H01L2224/45015 ,  H01L2224/48106 ,  H01L2224/48108 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49173 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1425 ,  H01L2924/1426 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H02M3/155 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/20752 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2224/05599

Abstract: A power supply system has a leadframe with leads and a pad. The pad surface facing a circuit board has a portion recessed with a depth and an outline suitable for attaching side-by-side the sync and the control FET semiconductor chips. The input terminal of the control FET and the grounded output terminal of the sync FET are coplanar with the un-recessed portion of the pad (switch node terminal) so that all terminals can be directly attached to contacts of a circuit board. A driver-and-control chip is vertically stacked to the opposite pad surface and encapsulated in a packaging compound.

Abstract translation: 电源系统具有带引线和焊盘的引线框架。 面对电路板的焊盘表面具有凹陷的部分，其深度和轮廓适合于并置并联和控制FET半导体芯片。 控制FET的输入端子和同步FET的接地输出端子与焊盘（开关节点端子）的未凹入部分共面，使得所有端子可以直接附接到电路板的触点。 驱动器和控制芯片垂直地堆叠到相对的焊盘表面并且封装在封装复合体中。

公开(公告)号：US09425132B2

公开(公告)日：2016-08-23

申请号：US14878408

申请日：2015-10-08

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Jonathan A. Noquil

IPC: H01L23/495 ,  H01L25/16 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065

CPC classification number: H01L23/49575 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/165 ,  H01L25/50 ,  H01L2224/27312 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/32147 ,  H01L2224/32148 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/4103 ,  H01L2224/41051 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48111 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/73271 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83455 ,  H01L2224/83464 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/8391 ,  H01L2224/84439 ,  H01L2224/84444 ,  H01L2224/84447 ,  H01L2224/84455 ,  H01L2224/84464 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/8491 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2224/92147 ,  H01L2224/92157 ,  H01L2224/9221 ,  H01L2224/92242 ,  H01L2224/92247 ,  H01L2224/92252 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1425 ,  H01L2924/14252 ,  H01L2924/1426 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/20752 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07811 ,  H01L2924/07812 ,  H01L2224/83447 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/85 ,  H01L2224/27

Abstract: A system has a leadframe with leads and a pad. The pad surface having a portion recessed with a depth and an outline suitable for attaching a semiconductor chip. A first chip is vertically stacked to the opposite pad surface. A clip is vertically stacked on the first chip and tied to a lead. A second chip has a terminal attached to the recessed portion and terminals co-planar with the un-recessed portion. A second chip is attached to the clip.

Abstract translation: 系统具有带引线和焊盘的引线框架。 焊盘表面具有凹陷的部分，其具有适于附接半导体芯片的深度和轮廓。 第一芯片垂直堆叠到相对的焊盘表面。 一个夹子垂直堆放在第一个芯片上并绑在一个引线上。 第二芯片具有附接到凹部的端子和与未凹部共同的端子。 第二个芯片连接到夹子上。

公开(公告)号：US09355991B2

公开(公告)日：2016-05-31

申请号：US14938465

申请日：2015-11-11

Applicant: Texas Instruments Incorporated

Inventor： Marie Denison ,  Brian Ashley Carpenter ,  Osvaldo Jorge Lopez ,  Juan Alejandro Herbsommer ,  Jonathan Noquil

IPC: H01L21/50 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L23/49575 ,  H01L21/50 ,  H01L21/561 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/84 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/072 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/29101 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40145 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2924/014 ,  H01L2924/20752

Abstract: A method for fabricating an electronic multi-output device. A substrate having a pad and pins is provided. A first chip is provided having a first and a second transistor integrated so that the first terminals of the transistors are merged into a common terminal on one chip surface and the patterned second and third terminals are on the opposite chip surface. The common first terminal is attached to the substrate pad. A driver and control chip is attached to the substrate pad adjacent to the first chip. The second terminals of the first and second transistors are connected by discrete first and second gang clips to respective substrate pins. A second chip is provided having a third and a fourth transistor integrated so that the second terminals of the transistors are merged into a common terminal on one chip surface. Patterned first and third terminals are on the opposite chip surface. The second chip is flipped to attach the first terminals vertically to the first and second gang clips. The third terminals are concurrently attached by discrete gang clips to respective pins. A common clip is attached to the common second terminal and connecting the common clip to a pin.

Abstract translation: 一种制造电子多输出装置的方法。 提供具有焊盘和引脚的基板。 提供第一芯片，其具有集成的第一和第二晶体管，使得晶体管的第一端子在一个芯片表面上合并成公共端子，并且图案化的第二和第三端子在相对的芯片表面上。 公共第一端子附接到衬底垫。 驱动器和控制芯片附接到与第一芯片相邻的衬底焊盘。 第一和第二晶体管的第二端子通过离散的第一和第二组合夹连接到相应的衬底引脚。 提供第二芯片，其具有集成的第三和第四晶体管，使得晶体管的第二端子在一个芯片表面上合并成公共端子。 图案化的第一和第三端子在相对的芯片表面上。 第二芯片被翻转以将第一终端垂直地附接到第一和第二组合夹。 第三端子通过离散的组夹同时附接到相应的引脚。 共同的夹子连接到公共第二端子并将公共夹子连接到销。

公开(公告)号：US20160133616A1

公开(公告)日：2016-05-12

申请号：US14737072

申请日：2015-06-11

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Walter Hans Paul Schroen ,  Jonathan Almeria Noquil ,  Thomas Eugene Grebs ,  Simon John Molloy

IPC: H01L25/16 ,  H01L31/042 ,  H01L31/0216 ,  H01L25/00 ,  H01L27/088 ,  H01L31/18 ,  H01L31/02 ,  H01L31/028 ,  H01L27/082

CPC classification number: H01L25/167 ,  H01L21/50 ,  H01L23/053 ,  H01L23/06 ,  H01L23/13 ,  H01L23/147 ,  H01L23/49844 ,  H01L24/83 ,  H01L25/18 ,  H01L25/50 ,  H01L27/082 ,  H01L27/088 ,  H01L29/0657 ,  H01L31/02008 ,  H01L31/02168 ,  H01L31/028 ,  H01L31/042 ,  H01L31/1804 ,  H01L31/1868 ,  H01L2224/83851 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/04642 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/10155 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/1425 ,  H01L2924/1427 ,  H01L2924/15

Abstract: A self-powered electronic system comprises a first chip (401) of single-crystalline semiconductor embedded in a second chip (302) of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container (330) bordered by ridges (331). The flat side (335) of the slab includes a heavily n-doped region (314) forming a pn-junction (315) with the p-type bulk. A metal-filled deep silicon via (350) through the p-type ridge (331) connects the n-region with the terminal (322) on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.

Abstract translation: 一种自供电的电子系统包括：嵌入第二芯片（302）中的单晶半导体的第一芯片（401），该第二芯片形成为与脊状接合的容器。 组装的芯片被嵌套，并形成电子器件，该电子器件依次组装在由p型掺杂的低级硅片形成的平板中，该片状物作为与脊（331）相邻的容器（330）。 板坯的平坦侧面（335）包括形成具有p型体积的pn结（315）的大量n掺杂区域（314）。 通过p型脊（331）的金属填充的深硅通孔（350）将p区域作为阳极将n区与作为阳极的阳极的脊表面上的端子（322）连接。 pn结上的电压用作器件的电源。

公开(公告)号：US20160064361A1

公开(公告)日：2016-03-03

申请号：US14938387

申请日：2015-11-11

Applicant: Texas Instruments Incorporated

Inventor： Marie Denison ,  Brian Ashley Carpenter ,  Osvaldo Jorge Lopez ,  Juan Alejandro Herbsommer ,  Jonathan Noquil

IPC: H01L25/065 ,  H01L23/495

CPC classification number: H01L23/49575 ,  H01L21/50 ,  H01L21/561 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/84 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/072 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/29101 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40145 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2924/014 ,  H01L2924/20752

Abstract: An electronic multi-output device has a substrate including a first pad, a second pad and a plurality of pins. A first chip with a first transistor has a first terminal on one chip surface and a second and third terminals on the opposite chip surface. The first chip with its first terminal is tied to the first pad. A second chip with a second transistor has a first terminal on one chip surface and a second and third terminals on the opposite chip surface. The second chip with its first terminal is tied to the second pad. The second terminals are connected by a discrete first metal clip and a second metal clip to respective substrate pins. A composite third chip has a third and a fourth transistor integrated so that the first terminals of the transistors are on one chip surface. The second terminals are merged into a common terminal. The patterned third terminals are on the opposite chip surface. The first terminals are vertically attached to the first and second metal clips, respectively. The common terminal is connected by a common clip to a substrate pin.

Abstract translation: 电子多输出装置具有包括第一垫，第二垫和多个销的基板。 具有第一晶体管的第一芯片在一个芯片表面上具有第一端子，在相对的芯片表面上具有第二和第三端子。 第一个芯片与第一个终端绑在第一个焊盘上。 具有第二晶体管的第二芯片在一个芯片表面上具有第一端子，在相对的芯片表面上具有第二和第三端子。 具有第一个终端的第二个芯片与第二个焊盘相连。 第二端子通过离散的第一金属夹和第二金属夹连接到相应的衬底引脚。 复合第三芯片具有集成的晶体管的第一端子在一个芯片表面上的第三和第四晶体管。 第二个终端被合并成一个公共终端。 图案化的第三端子在相对的芯片表面上。 第一端子分别垂直地附接到第一和第二金属夹。 公共端子通过公共夹子连接到基板引脚。

公开(公告)号：US09214415B2

公开(公告)日：2015-12-15

申请号：US14181966

申请日：2014-02-17

Applicant: Texas Instruments Incorporated

Inventor： Marie Denison ,  Brian Ashley Carpenter ,  Osvaldo Jorge Lopez ,  Juan Alejandro Herbsommer ,  Jonathan Noquil

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/49575 ,  H01L21/50 ,  H01L21/561 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/84 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/072 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/29101 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40145 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2924/014 ,  H01L2924/20752

Abstract: A packaged multi-output converter (200) comprising a leadframe with a chip pad (201) as ground terminal and a plurality of leads (202) including the electrical input terminal (203); a first FET chip (sync chip, 220) with its source terminal affixed to the leadframe and on its opposite surface a first drain terminal (221) positioned adjacent to a second drain terminal (222), the drain terminals connected respectively by a first (241) and a second (242) metal clip to a first (204) and second (205) output lead; a second FET chip (control chip, 211), positioned vertically over the first drain terminal, with its source terminal attached onto the first clip; a third FET chip (control chip, 212), positioned vertically over the second drain terminal, with its source terminal attached onto the second clip; and the drain terminals (213, 214) of the second and third chips attached onto a third metal clip (260) connected to the input lead (203).

Abstract translation: 一种封装的多输出转换器（200），包括具有作为接地端子的芯片焊盘（201）的引线框和包括所述电输入端子（203）的多个引线（202）; 第一FET芯片（同步芯片，220），其源极端子固定到引线框架，并且在其相对表面上与第二漏极端子（222）相邻定位的第一漏极端子（221），漏极端子分别由第一（ 241）和第二（242）金属夹到第一（204）和第二（205）输出引线; 位于第一漏极端子上方的第二FET芯片（控制芯片211），其源极端子附接到第一夹子上; 第三FET芯片（控制芯片212），其垂直地位于第二漏极端子上，其源极端子附接到第二夹子上; 和连接到连接到输入引线（203）的第三金属夹（260）上的第二和第三芯片的漏极端子（213,214）。

公开(公告)号：US09184121B2

公开(公告)日：2015-11-10

申请号：US14173147

申请日：2014-02-05

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Johathan A. Noquil

IPC: H01L23/495 ,  H01L25/16 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065

CPC classification number: H01L23/49575 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/165 ,  H01L25/50 ,  H01L2224/27312 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/32147 ,  H01L2224/32148 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/4103 ,  H01L2224/41051 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48111 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/73271 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83455 ,  H01L2224/83464 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/8391 ,  H01L2224/84439 ,  H01L2224/84444 ,  H01L2224/84447 ,  H01L2224/84455 ,  H01L2224/84464 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/8491 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2224/92147 ,  H01L2224/92157 ,  H01L2224/9221 ,  H01L2224/92242 ,  H01L2224/92247 ,  H01L2224/92252 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1425 ,  H01L2924/14252 ,  H01L2924/1426 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/20752 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07811 ,  H01L2924/07812 ,  H01L2224/83447 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/85 ,  H01L2224/27

Abstract: A power supply system (200) has a QFN leadframe with leads and a pad (201, switch node terminal); a pad surface having a portion recessed with a depth (270) and an outline suitable for attaching a semiconductor chip. A first FET chip (220) is vertically stacked to the opposite pad surface. A clip (240) is vertically stacked on the first FET chip and tied to a lead (202, grounded output terminal). A second FET chip (210) has its source terminal attached to the recessed portion and its drain (210a, input terminal) and gate (210b) terminals co-planar with the un-recessed portion. A driver-and-controller chip (230) is attached to the clip. Packaging compound (290) encapsulates the parts but leaves a pad surface and the drain and gate terminals of the second FET chip un-encapsulated.

Abstract translation: 电源系统（200）具有带导线和焊盘（201，开关节点端子）的QFN引线框架; 垫表面，其具有凹入深度（270）的部分和适合于附接半导体芯片的轮廓。 第一FET芯片（220）垂直地堆叠到相对的焊盘表面。 夹子（240）垂直堆叠在第一FET芯片上并连接到引线（202，接地输出端子）。 第二FET芯片（210）的源极端子连接到凹部，其漏极（210a，输入端子）和栅极（210b）端子与未凹入部分共面。 驱动器和控制器芯片（230）附接到夹子。 包装化合物（290）封装部件但留下焊盘表面，并且第二FET芯片的漏极和栅极端子未封装。

公开(公告)号：US20140306332A1

公开(公告)日：2014-10-16

申请号：US14181966

申请日：2014-02-17

Applicant: Texas Instruments Incorporated

Inventor： Marie Denison ,  Brian Ashley Carpenter ,  Osvaldo Jorge Lopez ,  Juan Alejandro Herbsommer ,  Jonathan Noquil

IPC: H01L23/495 ,  H01L21/50 ,  H01L23/48

CPC classification number: H01L23/49575 ,  H01L21/50 ,  H01L21/561 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/84 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/072 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/29101 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40145 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2924/014 ,  H01L2924/20752

Abstract: A packaged multi-output converter (200) comprising a leadframe with a chip pad (201) as ground terminal and a plurality of leads (202) including the electrical input terminal (203); a first FET chip (sync chip, 220) with its source terminal affixed to the leadframe and on its opposite surface a first drain terminal (221) positioned adjacent to a second drain terminal (222), the drain terminals connected respectively by a first (241) and a second (242) metal clip to a first (204) and second (205) output lead; a second FET chip (control chip, 211), positioned vertically over the first drain terminal, with its source terminal attached onto the first clip; a third FET chip (control chip, 212), positioned vertically over the second drain terminal, with its source terminal attached onto the second clip; and the drain terminals (213, 214) of the second and third chips attached onto a third metal clip (260) connected to the input lead (203).

Abstract translation: 一种封装的多输出转换器（200），包括具有作为接地端子的芯片焊盘（201）的引线框和包括所述电输入端子（203）的多个引线（202）; 第一FET芯片（同步芯片，220），其源极端子固定到引线框架，并且在其相对表面上与第二漏极端子（222）相邻定位的第一漏极端子（221），漏极端子分别由第一（ 241）和第二（242）金属夹到第一（204）和第二（205）输出引线; 位于第一漏极端子上方的第二FET芯片（控制芯片211），其源极端子附接到第一夹子上; 第三FET芯片（控制芯片212），其垂直地位于第二漏极端子上，其源极端子附接到第二夹子上; 和连接到连接到输入引线（203）的第三金属夹（260）上的第二和第三芯片的漏极端子（213,214）。

公开(公告)号：US11817375B2

公开(公告)日：2023-11-14

申请号：US16274562

申请日：2019-02-13

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Tianyi Luo ,  Jonathan Almeria Noquil

IPC: H01L23/49 ,  H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49541 ,  H01L21/4828 ,  H01L21/56 ,  H01L23/3135 ,  H01L23/49582

Abstract: A method of making a semiconductor device includes separating a conductive structure of a leadframe into interior conductive leads using an etching process. The method includes forming a first molded structure by applying a first molding compound to a leadframe having a conductive structure, separating the conductive structure into at least two interior contact portions, attaching a semiconductor die to at least one of the interior contact portions, the at least two interior contact portions being supported by the first molding compound, and forming a second molded structure by applying a second molding compound to at least part of the semiconductor die and at least two interior contact portions.