公开(公告)号：US09711407B2

公开(公告)日：2017-07-18

申请号：US12970602

申请日：2010-12-16

申请人： Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  J. L. de Jong ,  Deepak C. Sekar ,  Paul Lim

发明人： Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  J. L. de Jong ,  Deepak C. Sekar ,  Paul Lim

IPC分类号： H01L21/822 ,  H01L21/84 ,  H01L21/683 ,  H01L23/00 ,  H01L23/525 ,  H01L23/544 ,  H01L25/065 ,  H01L27/02 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L27/118 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  G06F17/50 ,  H01L21/762 ,  H01L21/8238 ,  H01L25/00 ,  H01L27/06 ,  H01L27/11 ,  H01L27/112 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/12 ,  H01L29/788 ,  H01L29/792 ,  H01L23/367 ,  H01L23/48

CPC分类号： H01L27/1266 ,  G06F17/5072 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5252 ,  H01L23/544 ,  H01L24/05 ,  H01L24/13 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/10802 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L27/1214 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7848 ,  H01L29/7881 ,  H01L29/792 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/0401 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01066 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/80001 ,  H01L2924/00012

摘要： A semiconductor device includes a first mono-crystallized layer including first transistors, and a first metal layer forming at least a portion of connections between the first transistors; and a second layer including second transistors, the second transistors including mono-crystalline material, the second layer overlying the first metal layer, wherein the first metal layer includes aluminum or copper, and wherein the second layer is less than one micron in thickness and includes logic cells.

公开(公告)号：US09029173B2

公开(公告)日：2015-05-12

申请号：US13276312

申请日：2011-10-18

申请人： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Ze'ev Wurman

发明人： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Ze'ev Wurman

IPC分类号： H01L21/48 ,  H01L23/48 ,  H01L21/84 ,  H01L27/02 ,  H01L27/06 ,  H01L29/78 ,  H01L27/088 ,  H01L27/092 ,  H01L27/108 ,  H01L29/786 ,  H01L27/11 ,  H01L27/115 ,  H01L27/118 ,  H01L27/12 ,  H01L23/544 ,  H01L21/683 ,  H01L21/66 ,  H01L45/00 ,  H01L27/24 ,  H01L21/762

CPC分类号： H01L21/6835 ,  H01L21/76254 ,  H01L21/84 ,  H01L21/845 ,  H01L22/22 ,  H01L23/481 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11803 ,  H01L27/1203 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/249 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/78696 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1683 ,  H01L2221/6835 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method for formation of a semiconductor device, the method including: providing a first mono-crystalline layer including first transistors and first alignment marks; providing an interconnection layer including aluminum or copper on top of the first mono-crystalline layer; and then forming a second mono-crystalline layer on top of the first mono-crystalline layer interconnection layer by using a layer transfer step, and then processing second transistors on the second mono-crystalline layer including a step of forming a gate dielectric, where at least one of the second transistors is a p-type transistor and at least one of the second transistors is an n-type transistor.

摘要翻译： 一种形成半导体器件的方法，所述方法包括：提供包括第一晶体管和第一对准标记的第一单晶层; 在所述第一单晶层的顶部上提供包括铝或铜的互连层; 然后通过使用层转移步骤在第一单晶层互连层的顶部上形成第二单晶层，然后在第二单晶层上处理包括形成栅极电介质的步骤的第二晶体管，其中在 第二晶体管中的至少一个是p型晶体管，并且第二晶体管中的至少一个是n型晶体管。

公开(公告)号：US09000557B2

公开(公告)日：2015-04-07

申请号：US13423200

申请日：2012-03-17

申请人： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

发明人： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC分类号： H01L23/532 ,  H01L21/822 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L21/8238

CPC分类号： H01L21/8221 ,  H01L21/823878 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1211 ,  H01L2224/16225 ,  H01L2224/73253

摘要： A device including a first layer of first transistors interconnected by at least one first interconnection layer, where the first interconnection layer includes copper or aluminum, a second layer including second transistors, the second layer overlaying the first interconnection layer, where the second layer is less than about 2 micron thick, where the second layer has a coefficient of thermal expansion; and a connection path connecting at least one of the second transistors to the first interconnection layer, where the connection path includes at least one through-layer via, where the at least one through-layer via is formed through and in direct contact with a source or drain of at least one of the second transistors.

摘要翻译： 一种器件，包括由至少一个第一互连层互连的第一层第一晶体管，其中第一互连层包括铜或铝，第二层包括第二晶体管，第二层覆盖第一互连层，其中第二层较少 大于约2微米厚，其中第二层具有热膨胀系数; 以及将所述第二晶体管中的至少一个连接到所述第一互连层的连接路径，其中所述连接路径包括至少一个贯通层通孔，其中所述至少一个贯通层通孔形成为通过并直接与源极接触 或漏极的至少一个第二晶体管。

公开(公告)号：US08975670B2

公开(公告)日：2015-03-10

申请号：US13555152

申请日：2012-07-22

申请人： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

发明人： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC分类号： H01L29/80 ,  H01L23/552 ,  H01L23/48 ,  H01L27/06

CPC分类号： H01L23/552 ,  H01L23/481 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device, including: a semiconductor substrate with a first layer including first transistors; a shield layer overlaying the first layer; a second layer overlaying the shield layer, the second layer including second transistors; wherein the shield layer is a mostly continuous layer with a plurality of regions for connections between the first transistors and the second transistors, and where the second transistors include monocrystalline regions.

摘要翻译： 一种半导体器件，包括：具有包括第一晶体管的第一层的半导体衬底; 覆盖第一层的屏蔽层; 覆盖所述屏蔽层的第二层，所述第二层包括第二晶体管; 其中所述屏蔽层是具有用于所述第一晶体管和所述第二晶体管之间的连接的多个区域的大部分连续的层，并且其中所述第二晶体管包括单晶区域。

公开(公告)号：US08901613B2

公开(公告)日：2014-12-02

申请号：US13041405

申请日：2011-03-06

申请人： Deepak C. Sekar ,  Zvi Or-Bach ,  Brian Cronquist

发明人： Deepak C. Sekar ,  Zvi Or-Bach ,  Brian Cronquist

IPC分类号： H01L27/10 ,  H01L23/367

CPC分类号： H01L23/367 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

摘要： A semiconductor device comprising power distribution wires wherein; a portion of said wires have thermal connection to the semiconductor layer and said thermal connection designed to conduct heat but to not conduct electricity.

摘要翻译： 一种包括配电线的半导体器件， 所述导线的一部分具有与半导体层的热连接，并且所述热连接被设计为传导热量但不导电。

公开(公告)号：US08709880B2

公开(公告)日：2014-04-29

申请号：US13314435

申请日：2011-12-08

申请人： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong

发明人： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong

IPC分类号： H01L21/82 ,  H01L21/8226 ,  H01L21/822 ,  H01L25/18 ,  H01L27/06

CPC分类号： H01L27/088 ,  G11C17/14 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/8226 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/544 ,  H01L24/14 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/092 ,  H01L27/105 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11803 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01066 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H03K17/687 ,  H03K19/0948 ,  H03K19/177 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A method of manufacturing semiconductor devices: providing a first device including a first die and second die, where the first die is diced from a first wafer, the second die is diced from a second wafer, the first die is connected to the second die using at least one through-silicon-via; providing a second device including a third die and fourth die, where the third die is diced from a third wafer, the fourth die is diced from a fourth wafer, the third die is connected to the fourth die using at least one through-silicon-via; where the first die includes a first functionality and the third die includes a second functionality, the first functionality is different than the second functionality, a majority of the masks used for processing the first wafer and the third wafer are the same; and the second die size is substantially different than the fourth die size.

摘要翻译： 一种制造半导体器件的方法：提供包括第一晶粒和第二晶粒的第一器件，其中第一晶粒从第一晶片切割，第二晶粒从第二晶片切割，第一晶粒使用 至少一个穿硅通孔; 提供包括第三管芯和第四管芯的第二器件，其中第三管芯从第三晶片切割，第四管芯从第四晶片切割，第三管芯使用至少一个穿硅硅片连接到第四管芯， 通过; 其中第一管芯包括第一功能，第三管芯包括第二功能，第一功能不同于第二功能，用于处理第一晶片和第三晶片的大多数掩模是相同的; 并且第二管芯尺寸基本上不同于第四管芯尺寸。

公开(公告)号：US08581349B1

公开(公告)日：2013-11-12

申请号：US13099010

申请日：2011-05-02

申请人： Deepak C. Sekar ,  Zvi Or-Bach ,  Brian Cronquist

发明人： Deepak C. Sekar ,  Zvi Or-Bach ,  Brian Cronquist

IPC分类号： H01L29/78 ,  H01L23/535

CPC分类号： H01L21/6835 ,  H01L21/84 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/092 ,  H01L27/10826 ,  H01L27/1108 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/1203 ,  H01L27/2436 ,  H01L27/249 ,  H01L29/785 ,  H01L29/78696 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/12032 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00

摘要： A 3D memory device, including: a first memory layer including a first memory transistor with side gates; a second memory layer including a second memory transistor with side gates; and a periphery circuits layer including logic transistors for controlling the memory, the periphery circuits are covered by a first isolation layer, where the first memory layer includes a first monolithically mono-crystal layer directly bonded to a second isolation layer, and the second memory layer includes a second monolithically mono-crystal layer directly bonded to the second isolation layer, and the first mono-crystal layer is bonded on top of the first isolation layer, and the second memory transistor is self-aligned to the first memory transistor.

摘要翻译： 一种3D存储器件，包括：第一存储层，包括具有侧栅极的第一存储晶体管; 第二存储层，包括具有侧栅极的第二存储晶体管; 以及包括用于控制存储器的逻辑晶体管的外围电路层，外围电路被第一隔离层覆盖，其中第一存储层包括直接接合到第二隔离层的第一单片单晶层，第二存储层 包括直接接合到第二隔离层的第二单晶单晶层，并且第一单晶层接合在第一隔离层的顶部，并且第二存储晶体管与第一存储晶体管自对准。

公开(公告)号：US20130193488A1

公开(公告)日：2013-08-01

申请号：US13683500

申请日：2012-11-21

申请人： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

发明人： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC分类号： H01L27/08

CPC分类号： H01L27/08 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/481 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/80001

摘要： A semiconductor device including: a first single crystal layer including first transistors, first alignment mark, and at least one metal layer, said at least one metal layer overlying said first single crystal layer, wherein the at least one metal layer includes copper or aluminum; and a second layer overlying the at least one metal layer; wherein the second layer includes second transistors, the second transistors include mono-crystal, the second transistors include P type transistors and N type transistors, and the second transistors are aligned to the first alignment mark with less than 40 nm alignment error.

摘要翻译： 一种半导体器件，包括：第一单晶层，包括第一晶体管，第一对准标记和至少一个金属层，所述至少一个金属层覆盖在所述第一单晶层上，其中所述至少一个金属层包括铜或铝; 以及覆盖所述至少一个金属层的第二层; 其中所述第二层包括第二晶体管，所述第二晶体管包括单晶，所述第二晶体管包括P型晶体管和N型晶体管，并且所述第二晶体管与所述第一对准标记对准，具有小于40nm的对准误差。

公开(公告)号：US20130095580A1

公开(公告)日：2013-04-18

申请号：US13276312

申请日：2011-10-18

申请人： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Ze'ev Wurman

发明人： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Ze'ev Wurman

IPC分类号： H01L21/71 ,  H01L21/66 ,  H01L21/76 ,  H01L21/82

CPC分类号： H01L21/6835 ,  H01L21/76254 ,  H01L21/84 ,  H01L21/845 ,  H01L22/22 ,  H01L23/481 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11803 ,  H01L27/1203 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/249 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/78696 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1683 ,  H01L2221/6835 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method for formation of a semiconductor device including a first mono-crystalline layer comprising first transistors and first alignment marks, the method comprising forming a doped layer within a wafer, forming a second mono-crystalline layer on top of the first mono-crystalline layer by transferring at least a portion of the doped layer using layer transfer step, and processing second transistors on the second mono-crystalline layer comprising a step of forming a gate dielectric, wherein the second transistors are horizontally oriented.

摘要翻译： 一种用于形成包括第一晶体管和第一对准标记的第一单晶层的半导体器件的方法，所述方法包括在晶片内形成掺杂层，在第一单晶层的顶部形成第二单晶层 通过使用层转移步骤转移至少一部分掺杂层，以及处理第二单晶层上的第二晶体管，包括形成栅极电介质的步骤，其中第二晶体管是水平取向的。

公开(公告)号：US08362482B2

公开(公告)日：2013-01-29

申请号：US13016313

申请日：2011-01-28

申请人： Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar ,  Paul Lim

发明人： Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar ,  Paul Lim

IPC分类号： H01L21/00 ,  H01L29/10 ,  H01L33/00 ,  H01L21/70

CPC分类号： H01L21/8221 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5252 ,  H01L24/05 ,  H01L24/13 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/10802 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L27/1214 ,  H01L27/1266 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7881 ,  H01L29/792 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/0401 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00015 ,  H01L2924/01031 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor device including a first layer including first transistors, wherein first logic circuits are constructed by the first transistors, and wherein the first logic circuits include at least one of Inverter, NAND gate, or NOR gate; and a second layer overlaying said first layer, the second layer including second transistors, wherein second logic circuits are constructed by the second transistors; wherein each logic circuit in the first logic circuits has inputs and at least one first output, the inputs are connected to the second logic circuits; wherein each logic circuit in the second logic circuits has a second output, and wherein the first transistors include first selectors adapted to selectively replace at least one of the at least one first outputs with at least one of the second outputs.

摘要翻译： 一种半导体器件，包括包括第一晶体管的第一层，其中第一逻辑电路由第一晶体管构成，并且其中第一逻辑电路包括反相器，非门或或非门中的至少一个; 以及覆盖所述第一层的第二层，所述第二层包括第二晶体管，其中第二逻辑电路由第二晶体管构成; 其中所述第一逻辑电路中的每个逻辑电路具有输入和至少一个第一输出，所述输入连接到所述第二逻辑电路; 其中所述第二逻辑电路中的每个逻辑电路具有第二输出，并且其中所述第一晶体管包括适于使用所述第二输出中的至少一个选择性地替换所述至少一个第一输出中的至少一个的第一选择器。