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公开(公告)号：US11682845B2
公开(公告)日：2023-06-20
申请号：US17373000
申请日：2021-07-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kwanghyun Baek , Seungtae Ko , Kijoon Kim , Juho Son , Sangho Lee , Youngju Lee , Jungyub Lee , Yonghun Cheon , Dohyuk Ha
CPC classification number: H01Q21/065 , H01Q1/246 , H01Q1/42 , H04B7/0413 , H05K1/181 , H05K9/0049 , H05K2201/042 , H05K2201/10015 , H05K2201/10098 , H05K2201/10719 , H05K2201/10734
Abstract: A communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT) are provided. The disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. According to the disclosure, an antenna module includes a first substrate layer on which at least one substrate is stacked; an antenna coupled to an upper end surface of the first substrate layer; a second substrate layer having an upper end surface coupled to a lower end surface of the first substrate layer and on which at least one substrate is stacked; and a radio frequency (RF) element coupled to a lower end surface of the second substrate layer.
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公开(公告)号：US11659656B2
公开(公告)日：2023-05-23
申请号：US17847233
申请日：2022-06-23
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Takahito Tomoda
CPC classification number: H05K1/0283 , H05K1/189 , H05K2201/09245 , H05K2201/09872 , H05K2201/09909 , H05K2201/1003 , H05K2201/10015 , H05K2201/10022 , H05K2201/10166
Abstract: A stretchable wiring board that includes a stretchable substrate having a first main surface with a first region, a second region adjacent the first region, and a third region adjacent the second region; a first stretchable wiring line on the first main surface and extending over the first region; an insulating layer extending over the first region and the second region; and a second stretchable wiring line extending over the first region, the second region, and the third region. When a thickness of the insulating layer is defined as Z2, and when a minimum value of a length of the second region in an extending direction of the second stretchable wiring line in a plan view of the stretchable wiring board is defined as Y, Y>Z2.
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43.发明公开公开(公告)号：US20230147809A1
公开(公告)日：2023-05-11
申请号：US17911698
申请日：2021-04-13
Applicant: Smoltek AB
Inventor： M Shafiqul Kabir , Vincent Desmaris , Anders Johansson , Ola Tiverman , Karl Lundahl , Rickard Andersson , Muhammad Amin Saleem , Maria Bylund , Victor Marknäs
Abstract: A MIM energy storage device comprising a bottom electrode; a plurality of electrically conductive vertical nanostructures; a bottom conduction-controlling layer conformally coating each nanostructure in the plurality of electrically conductive vertical nanostructures; and a layered stack of alternating conduction-controlling layers and electrode layers conformally coating the bottom conduction-controlling layer, the layered stack including at least a first odd-numbered electrode layer at a bottom of the layered stack, a first odd-numbered conduction-controlling layer directly on the first odd-numbered electrode layer, and a first even-numbered electrode layer directly on the first odd-numbered conduction-controlling layer. Each even-numbered electrode layer in the layered stack is electrically conductively connected to the bottom electrode; and each odd-numbered electrode layer in the layered stack is electrically conductively connected to any other odd-numbered electrode layer in the layered stack.
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44.发明申请公开(公告)号：US20190254166A1
公开(公告)日：2019-08-15
申请号：US16261679
申请日：2019-01-30
Applicant: Delta Electronics (Shanghai) CO., LTD
Inventor： Pengkai JI , Jianhong ZENG , Yu ZHANG , Shouyu HONG , Jinping ZHOU , BAU-RU LU
CPC classification number: H05K1/142 , H02M3/07 , H02M3/158 , H02M3/33576 , H05K1/0216 , H05K1/117 , H05K1/181 , H05K2201/048 , H05K2201/09036 , H05K2201/09045 , H05K2201/10015 , H05K2201/1003 , H05K2201/10037 , H05K2201/10545
Abstract: The present disclosure provides a power supply module used in a smart terminal and a power supply module assembly structure, the power supply module includes a substrate having first and second surfaces opposite to each other; a power passive element, an active element and a plurality of first conductive parts disposed at the substrate; the power passive element being independently disposed on the first surface of the substrate as a whole; wherein a maximum height of the power passive element disposed on the first surface of the substrate is greater than a sum of a maximum height of an element disposed on the second surface of the substrate and an half of the thickness of the substrate.
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公开(公告)号：US20190244760A1
公开(公告)日：2019-08-08
申请号：US16389245
申请日：2019-04-19
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Sang Soo PARK , Young Ghyu AHN , Hwi Dae KIM
CPC classification number: H01G4/30 , H01G4/012 , H01G4/12 , H01G4/232 , H01G4/236 , H01G4/248 , H05K1/111 , H05K1/181 , H05K2201/10015 , H05K2201/10636 , Y02P70/611
Abstract: A multilayer ceramic electronic component includes a body with a plurality of first and second internal electrodes alternately arranged with dielectric layers interposed therebetween. There may be M each of third and fourth external electrodes on opposing sides of the body, where M is greater than or equal to 3 and all external electrodes have different polarities than the adjacent external electrodes. There may be N via electrodes penetrating through the body, where N is greater than or equal to 3 and the via electrodes are connected to either of the first or second internal electrodes. The multilayer ceramic electronic component may achieve low equivalent series inductance (ESL) characteristics and may reduce the mounting area on the circuit board.
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Patent Agency Ranking
46.发明申请公开(公告)号：US20190240482A1
公开(公告)日：2019-08-08
申请号：US16385338
申请日：2019-04-16
Applicant: Greatbatch Ltd.
Inventor： Robert A. Stevenson , Christine A. Frysz , Richard L. Brendel
IPC: A61N1/08 , H05K1/18 , H05K9/00 , H03H1/00 , H01R13/7195 , H01G4/40 , A61N1/37 , A61N1/375 , H01G4/35 , H01G4/06 , H05K5/00 , H03H7/01
CPC classification number: A61N1/08 , A61N1/086 , A61N1/3718 , A61N1/375 , A61N1/3754 , H01G4/06 , H01G4/35 , H01G4/40 , H01R13/7195 , H03H1/0007 , H03H7/1766 , H03H2001/0042 , H03H2001/0085 , H05K1/181 , H05K5/0095 , H05K9/00 , H05K999/99 , H05K2201/10015
Abstract: A three-terminal flat-through EMI/energy dissipating filter comprises an active electrode plate through which a circuit current passes between a first terminal and a second terminal, a first shield plate on a first side of the active electrode plate, and second shield plate on a second side of the active electrode plate opposite the first shield plate. The first and second shield plates are conductively coupled to a grounded third terminal. Both the effective capacitance area or overlapping surface area of the active electrode plate and the surrounding ground shield plates and the dielectric constant of the insulating layers between the active electrode plate and the ground shield plates is raised to achieve a higher capacitance value for the three-terminal flat-through capacitor.
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公开(公告)号：US20190215964A1
公开(公告)日：2019-07-11
申请号：US16327435
申请日：2016-09-27
Applicant: Intel Corporation
Inventor： Brian J. Long
CPC classification number: H05K1/186 , H01R12/721 , H05K1/111 , H05K1/117 , H05K1/141 , H05K1/181 , H05K1/185 , H05K3/284 , H05K3/34 , H05K3/368 , H05K3/4015 , H05K2201/042 , H05K2201/10015 , H05K2201/10022 , H05K2201/1003 , H05K2201/10159 , H05K2201/10378 , H05K2201/10545 , H05K2201/10734 , H05K2203/0228 , H05K2203/107 , H05K2203/1316 , H05K2203/1327
Abstract: Aspects of the disclosure are directed to an edge card that includes a printed circuit board having a top side and a bottom side. The top side of the printed circuit board can include one or more top-side circuit components, and a plurality of top-side metal contact fingers, at least some of the top-side metal contact fingers electrically connected to at least one of the one or more circuit components. The bottom side of the printed circuit board can include one or more bottom-side circuit components. The bottom side of the printed circuit board can also include a substrate interposer having a top side and a bottom side. The top side of the substrate interposer can include one or more passive circuit components at least partially embedded in the substrate interposer, and one or more solder balls arranged around the one or more passive circuit components.
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公开(公告)号：US20190199232A1
公开(公告)日：2019-06-27
申请号：US16289758
申请日：2019-03-01
Applicant: Delta Electronics (Shanghai) CO., LTD
Inventor： Jianhong ZENG , Xiaoni XIN
IPC: H02M7/00 , H02M3/335 , H05K1/11 , H05K7/06 , H05K7/02 , H05K1/18 , H05K1/14 , H01F27/40 , H05K1/02 , H01F27/24 , H05K1/16 , H01F27/28 , H02M7/04
CPC classification number: H02M7/003 , H01F27/24 , H01F27/28 , H01F27/2804 , H01F27/306 , H01F27/40 , H01F2027/408 , H02M3/33576 , H02M7/04 , H02M2001/0048 , H05K1/0203 , H05K1/0254 , H05K1/111 , H05K1/115 , H05K1/142 , H05K1/145 , H05K1/165 , H05K1/181 , H05K1/182 , H05K7/026 , H05K7/06 , H05K2201/086 , H05K2201/10015 , H05K2201/1003 , H05K2201/10166 , H05K2201/10174 , Y02B70/1491
Abstract: A converter module includes: a system board; and an isolated rectifier unit connected with the system board via at least one pin, the isolated rectifier unit including: a system board; a circuit module; and an isolated rectifier unit arranged adjacent to the circuit module and connected with the system board; wherein the isolated rectifier unit includes: a magnetic core comprising at least one core column parallel to the system board and two cover plates provided at both ends of the core column; and multiple carrier board units provided between the two cover plates and perpendicular to the system board, wherein each of the carrier board units comprises at least one via hole, at least one primary winding, at least one secondary winding and at least one switch connected with the at least one secondary winding.
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49.发明申请公开(公告)号：US20190172902A1
公开(公告)日：2019-06-06
申请号：US16267142
申请日：2019-02-04
Applicant: STATS ChipPAC Pte. Ltd.
Inventor： JinHee Jung , HyungSang Park , SungSoo Kim
IPC: H01L49/02 , H05K1/18 , H01L23/538 , H01L21/683 , H01L23/00
CPC classification number: H01L28/40 , H01L21/486 , H01L21/6835 , H01L23/49827 , H01L23/50 , H01L23/5389 , H01L24/19 , H01L24/25 , H01L2221/68345 , H01L2224/04105 , H01L2224/2518 , H01L2224/32225 , H01L2224/82031 , H01L2224/82039 , H01L2224/82047 , H01L2224/83005 , H01L2224/92144 , H05K1/185 , H05K3/4664 , H05K2201/10015
Abstract: A semiconductor device comprises a first conductive layer. A second conductive layer is formed over the first conductive layer. A semiconductor component is disposed over the first conductive layer. The second conductive layer lies in a plane between a top surface of the semiconductor component and a bottom surface of the semiconductor component. A third conductive layer is formed over the semiconductor component opposite the first conductive layer. The semiconductor device includes a symmetrical structure. A first insulating layer is formed between the first conductive layer and semiconductor component. A second insulating layer is formed between the semiconductor component and third conductive layer. A height of the first insulating layer between the first conductive layer and semiconductor component is between 90% and 110% of a height of the second insulating layer between the semiconductor component and third conductive layer. The semiconductor component includes a passive device.
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50.发明申请公开(公告)号：US20190164691A1
公开(公告)日：2019-05-30
申请号：US16263761
申请日：2019-01-31
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Young Heon OH , Se Hwan BONG , Young Ha KIM , Dong Gun KIM
CPC classification number: H01G4/005 , H01G4/012 , H01G4/12 , H01G4/228 , H01G4/232 , H01G4/30 , H05K1/181 , H05K2201/10015 , H05K2201/10636 , Y02P70/611
Abstract: A multilayer ceramic capacitor with decreased high voltage stress defects and a board having the same may include a body formed by stacking a plurality of dielectric layers and a plurality of first and second internal electrodes in a width direction, the first and second internal electrodes including body portions overlapping each other and lead portions exposed to a mounting surface of the body and disposed to be spaced apart from each other, respectively; and first to third external electrodes disposed on the mounting surface of the capacitor body to be connected to the lead portions, respectively, wherein the body portions of the first and second internal electrodes have different areas from each other.
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