公开(公告)号：US20120133048A1

公开(公告)日：2012-05-31

申请号：US13235369

申请日：2011-09-17

Applicant: Ho-Jin LEE ,  Tae-Je CHO ,  Dong-Hyeon JANG ,  Ho-Geon SONG ,  Se-Young JEONG ,  Un-Byoung KANG ,  Min-Seung YOON

Inventor： Ho-Jin LEE ,  Tae-Je CHO ,  Dong-Hyeon JANG ,  Ho-Geon SONG ,  Se-Young JEONG ,  Un-Byoung KANG ,  Min-Seung YOON

IPC: H01L23/48

CPC classification number: H01L23/49844 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/525 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/05009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/15311

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

Abstract translation: 在一个实施例中，半导体器件包括具有第一表面的半导体衬底和与第一表面相对的第二表面。 第二表面限定再分布沟槽。 基板具有贯穿其中的通孔。 半导体器件还包括设置在通孔中的贯通孔。 通孔可以包括依次形成在通孔的内壁上的通孔绝缘层，阻挡层。 通孔还可以包括邻近阻挡层的导电连接器。 半导体器件还包括形成在衬底的第二表面上的绝缘层图案。 绝缘层图案限定了暴露通孔的顶表面的区域的开口。 半导体器件包括设置在沟槽中并与通孔电连接的再分配层。 绝缘层图案与导电连接器的区域重叠。

公开(公告)号：US07855144B2

公开(公告)日：2010-12-21

申请号：US11589717

申请日：2006-10-31

Applicant: Soon-bum Kim ,  Sung-min Sim ,  Dong-hyeon Jang ,  Jae-sik Chung ,  Se-yong Oh

Inventor： Soon-bum Kim ,  Sung-min Sim ,  Dong-hyeon Jang ,  Jae-sik Chung ,  Se-yong Oh

IPC: H01L21/44

CPC classification number: H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/01028

Abstract: Provided is a method of forming conductors (e.g., metal lines and/or bumps) for semiconductor devices and conductors formed from the same. First and second seed metal layers may be formed. At least one mask may be formed on a portion on which a conductor is to be formed. An exposed portion may be oxidized. The oxidized portion may be removed. A conductive structure may be formed on an upper surface of a portion which is not oxidized. The conductors may be metal lines and/or bumps. The conductive structures may be solder balls.

Abstract translation: 提供了形成半导体器件的导体（例如金属线和/或凸块）以及由其形成的导体的方法。 可以形成第一和第二种子金属层。 至少一个掩模可以形成在其上将形成导体的部分上。 暴露部分可能被氧化。 可以除去氧化部分。 可以在未被氧化的部分的上表面上形成导电结构。 导体可以是金属线和/或凸块。 导电结构可以是焊球。

公开(公告)号：US07545027B2

公开(公告)日：2009-06-09

申请号：US11448772

申请日：2006-06-08

Applicant: Hyun-Soo Chung ,  In-Young Lee ,  Dong-Hyeon Jang ,  Myeong-Soon Park ,  Dong-Ho Lee

Inventor： Hyun-Soo Chung ,  In-Young Lee ,  Dong-Hyeon Jang ,  Myeong-Soon Park ,  Dong-Ho Lee

IPC: H01L23/02

CPC classification number: H01L23/3114 ,  H01L23/525 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/0401 ,  H01L2224/10126 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/3025

Abstract: A wafer level package may include a semiconductor substrate supporting an electrode pad. A first insulating layer may be provided on the semiconductor substrate. The first insulating layer may include a first opening through which the electrode pad may be exposed. A seed metal layer may be provided on an entire surface of the first insulating layer. A redistribution interconnection metal layer may be provided on the seed metal layer. A second insulating layer may be provided on the redistribution interconnection metal layer. The second insulating layer may have a second opening spaced from the first opening to expose a portion of the redistribution interconnection metal layer. The second insulating layer may surround the redistribution interconnection metal layer. An unwanted portion of seed metal layer may be removed using the second insulating layer as an etch mask.

Abstract translation: 晶片级封装可以包括支撑电极焊盘的半导体衬底。 第一绝缘层可以设置在半导体衬底上。 第一绝缘层可以包括第一开口，电极焊盘可以暴露在第一开口中。 种子金属层可以设置在第一绝缘层的整个表面上。 再分布互连金属层可以设置在种子金属层上。 第二绝缘层可以设置在再分布互连金属层上。 第二绝缘层可以具有与第一开口间隔开的第二开口，以暴露再分布互连金属层的一部分。 第二绝缘层可以包围再分布互连金属层。 可以使用第二绝缘层作为蚀刻掩模去除种子金属层的不需要的部分。

公开(公告)号：US07300864B2

公开(公告)日：2007-11-27

申请号：US10911672

申请日：2004-08-05

Applicant: Keum-Hee Ma ,  Se-Young Jeong ,  Dong-Hyeon Jang ,  Gu-Sung Kim

Inventor： Keum-Hee Ma ,  Se-Young Jeong ,  Dong-Hyeon Jang ,  Gu-Sung Kim

IPC: H01L21/44

CPC classification number: H01L24/12 ,  H01L24/11 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A solder bump structure may be formed using a dual exposure technique of a photoresist, which may be a positive photoresist. The positive photoresist may be coated on an IC chip. First openings may be formed at first exposed regions of the photoresist by a first exposure process. Metal projections may be formed in the first openings. A second opening may be formed at a second exposed region of the photoresist by a second exposure process. The second exposed region may include non-exposed regions defined by the first exposure process. A solder material may fill the second opening and may be reflowed to form a solder bump. The metal projections may be embedded within the solder bump.

Abstract translation: 可以使用可以是正性光致抗蚀剂的光致抗蚀剂的双曝光技术来形成焊料凸块结构。 正光致抗蚀剂可以涂覆在IC芯片上。 可以通过第一曝光工艺在光致抗蚀剂的第一曝光区域处形成第一开口。 金属突起可以形成在第一开口中。 可以通过第二曝光工艺在光致抗蚀剂的第二曝光区域处形成第二开口。 第二曝光区域可以包括由第一曝光工艺限定的非曝光区域。 焊料材料可以填充第二开口并且可以回流以形成焊料凸块。 金属突起可以嵌入在焊料凸块内。

公开(公告)号：US20070264745A1

公开(公告)日：2007-11-15

申请号：US11878220

申请日：2007-07-23

Applicant: Yong-Chai Kwon ,  Kang-Wook Lee ,  Gu-Sung Kim ,  Seong-Il Han ,  Keum-Hee Ma ,  Suk-Chae Kang ,  Dong-Hyeon Jang

Inventor： Yong-Chai Kwon ,  Kang-Wook Lee ,  Gu-Sung Kim ,  Seong-Il Han ,  Keum-Hee Ma ,  Suk-Chae Kang ,  Dong-Hyeon Jang

IPC: H01L31/18

CPC classification number: H01L27/14618 ,  H01L27/1464 ,  H01L27/14685 ,  H01L2224/48091 ,  H04N5/2257 ,  H01L2924/00014

Abstract: An image sensor device including a protective plate may be manufactured from an image sensor chip having an active surface and a back surface opposite to the active surface. The image sensor chip may include chip pads formed in a peripheral region of the active surface, a microlens formed in a central region of the active surface and an intermediate region between the peripheral and central regions. A protective plate may be attached to the intermediate region of the active surface of the image sensor chip using an adhesive pattern that is sized and configured to maintain a separation distance between the protective plate and the microlens formed on the image sensor chip. Conductive plugs, formed before, during or after the manufacture of the image sensor chip circuitry may provide electrical connection between the chip pads and external connectors.

Abstract translation: 包括保护板的图像传感器装置可以由具有与活性表面相对的活性表面和背面的图像传感器芯片制造。 图像传感器芯片可以包括形成在有源表面的周边区域中的芯片焊盘，形成在有源表面的中心区域中的微透镜和在周边区域和中心区域之间的中间区域。 可以使用粘合剂图案将保护板附接到图像传感器芯片的有效表面的中间区域，该粘合剂图案的尺寸和构造用于保持保护板和形成在图像传感器芯片上的微透镜之间的间隔距离。 在图像传感器芯片电路制造之前，期间或之后形成的导电插塞可以提供芯片焊盘和外部连接器之间的电连接。

公开(公告)号：US07276799B2

公开(公告)日：2007-10-02

申请号：US10890995

申请日：2004-07-15

Applicant: Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-Sik Chung

Inventor： Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-Sik Chung

IPC: H01L23/48

CPC classification number: H01L25/50 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05569 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  Y02P80/30 ,  Y10S438/977 ,  Y10T436/104998 ,  Y10T436/108331 ,  Y10T436/17 ,  Y10T436/175383 ,  H01L2224/81 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip stack package is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting lines. A lower chip is then attached and connected to a substrate, which may be a test wafer, and an upper chip is attached and connected to the lower chip, the electrical connections being achieved through their respective connection vias. In addition to the connection vias, the chip stack package may include connection bumps formed between vertically adjacent chips and/or the lower chip and the substrate. The preferred substrate is a test wafer that allows the attached chips to be tested, and replaced if faulty, thereby ensuring that each layer of stacked chips includes only “known-good die” before the next layer of chips is attached thereby increasing the production rate and improving the yield.

Abstract translation: 通过在与芯片相邻的划线中形成连接通孔并且使用重新布线将连接器件芯片焊盘连接到连接通孔，在晶片级制造芯片堆叠封装。 然后将下部芯片连接并连接到可以是测试晶片的衬底，并且上部芯片被附接并连接到下部芯片，电连接通过它们各自的连接通孔来实现。 除了连接通孔之外，芯片堆叠封装可以包括在垂直相邻的芯片和/或下部芯片和衬底之间形成的连接凸块。 优选的基板是测试晶片，其允许附接的芯片被测试并且如果有故障则被替换，从而确保每层堆叠的芯片仅在连接下一层芯片之前仅包括“已知的芯片”，从而提高生产率 并提高产量。

公开(公告)号：US07274097B2

公开(公告)日：2007-09-25

申请号：US11137803

申请日：2005-05-26

Applicant: Seung-Duk Baek ,  Dong-Hyeon Jang ,  Jong-Joo Lee

Inventor： Seung-Duk Baek ,  Dong-Hyeon Jang ,  Jong-Joo Lee

IPC: H01L23/02 ,  H01L21/44

CPC classification number: H01L24/10 ,  H01L21/76802 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A semiconductor device package includes a substrate, first and second chip pads spaced apart over a surface of the substrate, and an insulating layer located over the surface of the substrate. The insulating layer includes a stepped upper surface defined by at least a lower reference potential line support surface portion, and an upper signal line support surface portion, where a thickness of the insulating layer at the lower reference potential line support surface portion is less than a thickness of the insulating layer at the upper signal line support surface portion. The package further includes a conductive reference potential line electrically connected to the first chip pad and located on the lower reference potential support surface portion of the insulating layer, a conductive signal line electrically connected to the second chip pad and located on the upper signal line support surface portion, and first and second external terminals electrically connected to the conductive reference potential line and the conductive signal line, respectively.

Abstract translation: 半导体器件封装包括衬底，在衬底的表面上间隔开的第一和第二芯片焊盘以及位于衬底表面上的绝缘层。 绝缘层包括由至少一个下参考电位线支撑表面部分限定的阶梯状上表面和上信号线支撑表面部分，其中下参考电位线支撑表面部分处的绝缘层的厚度小于 上部信号线支撑表面部分处的绝缘层的厚度。 所述封装还包括电连接到所述第一芯片焊盘并且位于所述绝缘层的下参考电位支撑表面部分上的导电参考电位线，电连接到所述第二芯片焊盘并位于所述上信号线支撑件上的导电信号线 表面部分以及分别电连接到导电参考电位线和导电信号线的第一和第二外部端子。

公开(公告)号：US20070176290A1

公开(公告)日：2007-08-02

申请号：US11717691

申请日：2007-03-14

Applicant: Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

Inventor： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L23/3114 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02165 ,  H01L2224/02335 ,  H01L2224/02351 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05569 ,  H01L2224/10125 ,  H01L2224/13006 ,  H01L2224/13011 ,  H01L2224/13018 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.

公开(公告)号：US20070108573A1

公开(公告)日：2007-05-17

申请号：US11448772

申请日：2006-06-08

Applicant: Hyun-Soo Chung ,  In-Young Lee ,  Dong-Hyeon Jang ,  Myeong-Soon Park ,  Dong-Ho Lee

Inventor： Hyun-Soo Chung ,  In-Young Lee ,  Dong-Hyeon Jang ,  Myeong-Soon Park ,  Dong-Ho Lee

IPC: H01L23/02

CPC classification number: H01L23/3114 ,  H01L23/525 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/0401 ,  H01L2224/10126 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/3025

Abstract: A wafer level package may include a semiconductor substrate supporting an electrode pad. A first insulating layer may be provided on the semiconductor substrate. The first insulating layer may include a first opening through which the electrode pad may be exposed. A seed metal layer may be provided on an entire surface of the first insulating layer. A redistribution interconnection metal layer may be provided on the seed metal layer. A second insulating layer may be provided on the redistribution interconnection metal layer. The second insulating layer may have a second opening spaced from the first opening to expose a portion of the redistribution interconnection metal layer. The second insulating layer may surround the redistribution interconnection metal layer. An unwanted portion of seed metal layer may be removed using the second insulating layer as an etch mask.

Abstract translation: 晶片级封装可以包括支撑电极焊盘的半导体衬底。 第一绝缘层可以设置在半导体衬底上。 第一绝缘层可以包括第一开口，电极焊盘可以暴露在第一开口中。 种子金属层可以设置在第一绝缘层的整个表面上。 再分布互连金属层可以设置在种子金属层上。 第二绝缘层可以设置在再分布互连金属层上。 第二绝缘层可以具有与第一开口间隔开的第二开口，以暴露再分布互连金属层的一部分。 第二绝缘层可以包围再分布互连金属层。 可以使用第二绝缘层作为蚀刻掩模去除种子金属层的不需要的部分。

公开(公告)号：US20070096341A1

公开(公告)日：2007-05-03

申请号：US11430900

申请日：2006-05-10

Applicant: Hyun-soo Chung ,  Dong-hyeon Jang ,  Dong-ho Lee ,  In-young Lee

Inventor： Hyun-soo Chung ,  Dong-hyeon Jang ,  Dong-ho Lee ,  In-young Lee

IPC: H01L23/52

CPC classification number: H01L23/3128 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/06136 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/92147 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19103 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: A ball grid array type board on chip package may include an integrated circuit chip having an active surface that supports a plurality of contact pads. An interposer may be adhered to the active surface of the integrated circuit chip. At least one hole may be provided through the interposer to expose the contact pads. A board, which may have a first surface supporting a plurality of metal lines, may have a second surface adhered to the interposer. The board may have an opening through which the contact pads may be exposed. A plurality of bonding wires may connect the contact pads to the metal lines through the opening.

Abstract translation: 球栅阵列型片上芯片封装可以包括具有支撑多个接触焊盘的有源表面的集成电路芯片。 插入器可以粘附到集成电路芯片的有源表面。 可以通过插入件提供至少一个孔以暴露接触垫。 可以具有支撑多个金属线的第一表面的板可以具有粘附到插入件的第二表面。 板可以具有开口，接触垫可以穿过该开口露出。 多个接合线可以通过开口将接触垫连接到金属线。