公开(公告)号：US07110631B2

公开(公告)日：2006-09-19

申请号：US11015901

申请日：2004-12-17

Applicant: Charles H. Joyner ,  Mark J. Missey ,  Radhakrishnan L. Nagarajan ,  Fred A. Kish, Jr.

Inventor： Charles H. Joyner ,  Mark J. Missey ,  Radhakrishnan L. Nagarajan ,  Fred A. Kish, Jr.

IPC: G02B6/10 ,  G02B6/12

CPC classification number: G02B6/12011 ,  G02B6/12016 ,  G02B6/12019 ,  G02B6/12023 ,  G02B6/132 ,  G02B6/42 ,  G02B2006/12097 ,  G02B2006/12176 ,  H01S5/026 ,  H01S5/0264 ,  H01S5/0265 ,  H01S5/0268 ,  H01S5/1014 ,  H01S5/2213 ,  H01S5/2231 ,  H01S5/227 ,  H01S5/4031 ,  H01S5/4087

Abstract: Disclosed is a method of adjusting a center channel wavelength of a group of channel wavelengths from of a plurality of modulated sources, integrated in a photonic integrated circuit (PIC), relative to the center of a wavelength passband of an optical combiner, such as an arrayed waveguide array (AWG), also integrated in the photonic integrated circuit (PIC) and optically coupled to outputs from the modulated sources.

Abstract translation: 公开了一种调整来自集成在光子集成电路（PIC）中的多个调制源的一组信道波长的中心信道波长相对于光合并器的波长通带的中心的方法，例如 阵列波导阵列（AWG），也集成在光子集成电路（PIC）中，并且光耦合到来自调制源的输出。

公开(公告)号：US07082231B2

公开(公告)日：2006-07-25

申请号：US11018630

申请日：2004-12-21

Applicant: Charles H. Joyner ,  Mark J. Missey ,  Fred A. Kish, Jr.

Inventor： Charles H. Joyner ,  Mark J. Missey ,  Fred A. Kish, Jr.

IPC: G02B6/12 ,  G02B6/28

CPC classification number: G02B6/12011 ,  G02B6/12016 ,  G02B6/12019 ,  G02B6/12023 ,  G02B6/132 ,  G02B6/42 ,  G02B2006/12097 ,  G02B2006/12176 ,  H01S5/026 ,  H01S5/0264 ,  H01S5/0265 ,  H01S5/0268 ,  H01S5/1014 ,  H01S5/2213 ,  H01S5/2231 ,  H01S5/227 ,  H01S5/4031 ,  H01S5/4087

Abstract: An optical waveguide device, power coupler, a star coupler, a MMI coupler, an arrayed waveguide grating (AWG) or an Echelle grating, having at least one free space region with a plurality of optical waveguides coupled as inputs and separated by channels having a angled bottom portion, the channels monotonically decreasing in size or shape in a direction toward the free space region and optically coupling with adjacent waveguides at the interface region between the optical waveguides and the free space region so that insertion loss at the interface region is substantially reduced.

Abstract translation: 光波导器件，功率耦合器，星形耦合器，MMI耦合器，阵列波导光栅（AWG）或Echelle光栅，具有至少一个自由空间区域，多个光波导耦合作为输入，并由具有 角度的底部部分，通道在朝向自由空间区域的方向上在尺寸或形状上单调减小，并且与光波导与自由空间区域之间的界面区域处的相邻波导光学耦合，使得界面区域处的插入损耗显着减小 。

公开(公告)号：US07076126B2

公开(公告)日：2006-07-11

申请号：US11018162

申请日：2004-12-21

Applicant: Charles H. Joyner ,  Mark J Missey ,  Radhakrishnan L. Nagarajan ,  Fred A. Kish, Jr.

Inventor： Charles H. Joyner ,  Mark J Missey ,  Radhakrishnan L. Nagarajan ,  Fred A. Kish, Jr.

IPC: G02B6/10 ,  G02B6/12

CPC classification number: G02B6/12011 ,  G02B6/12016 ,  G02B6/12019 ,  G02B6/12023 ,  G02B6/132 ,  G02B6/42 ,  G02B2006/12097 ,  G02B2006/12176 ,  H01S5/026 ,  H01S5/0264 ,  H01S5/0265 ,  H01S5/0268 ,  H01S5/1014 ,  H01S5/2213 ,  H01S5/2231 ,  H01S5/227 ,  H01S5/4031 ,  H01S5/4087

Abstract: A photonic integrated circuit (PIC) comprises a plurality of integrated optically coupled components formed in a surface of the PIC and a passivating layer overlies at least a portion of the PIC surface. The overlying passivating layer comprises a material selected from the group consisting of BCB, ZnS and ZnSe. Also, when the circuits are PIC chips are die in the semiconductor wafer, a plurality of linear cleave streets are formed in a wafer passivation layer where a pattern of the cleave streets define separate PIC chips in the wafer for their subsequent singulation from the wafer.

Abstract translation: 光子集成电路（PIC）包括形成在PIC的表面中的多个集成的光耦合部件，钝化层覆盖PIC表面的至少一部分。 上覆钝化层包括选自BCB，ZnS和ZnSe的材料。 此外，当电路是PIC芯片在半导体晶片中死亡时，在晶片钝化层中形成多个线性切割街道，其中劈裂街道的图案在晶片中限定了用于随后从晶片分离的单独的PIC芯片。

公开(公告)号：US07060517B2

公开(公告)日：2006-06-13

申请号：US11018161

申请日：2004-12-21

Applicant: Charles H. Joyner ,  Mark J. Missey ,  Radhakrishnan L. Nagarajan ,  Fred A. Kish, Jr.

Inventor： Charles H. Joyner ,  Mark J. Missey ,  Radhakrishnan L. Nagarajan ,  Fred A. Kish, Jr.

IPC: H01L21/00

CPC classification number: G02B6/12011 ,  G02B6/12016 ,  G02B6/12019 ,  G02B6/12023 ,  G02B6/132 ,  G02B6/42 ,  G02B2006/12097 ,  G02B2006/12176 ,  H01S5/026 ,  H01S5/0264 ,  H01S5/0265 ,  H01S5/0268 ,  H01S5/1014 ,  H01S5/2213 ,  H01S5/2231 ,  H01S5/227 ,  H01S5/4031 ,  H01S5/4087

Abstract: A method for reducing insertion loss in a transition region between a plurality of input or output waveguides to a free space coupler region in a photonic integrated circuit (PIC) includes the steps of forming a passivation layer over the waveguides and region and forming the passivation overlayer such that it monotonically increases in thickness through the transition region to the free space coupler region.

公开(公告)号：US07043109B2

公开(公告)日：2006-05-09

申请号：US11242518

申请日：2005-10-03

Applicant: Fred A. Kish, Jr. ,  Charles H. Joyner ,  Mark J. Missey ,  Frank H. Peters ,  Radhakrishnan L. Nagarajan ,  Richard P. Schneider

Inventor： Fred A. Kish, Jr. ,  Charles H. Joyner ,  Mark J. Missey ,  Frank H. Peters ,  Radhakrishnan L. Nagarajan ,  Richard P. Schneider

IPC: G02B6/12 ,  H01L21/66 ,  G01N21/00

CPC classification number: G02B6/12011 ,  B82Y20/00 ,  G01R31/31728 ,  G01R31/318511 ,  G02B6/12004 ,  G02B6/12007 ,  G02B6/12019 ,  G02B6/12021 ,  G02B6/12023 ,  G02B6/12026 ,  G02B6/12028 ,  G02B6/12033 ,  G02B6/131 ,  G02B6/136 ,  G02B6/4204 ,  G02F1/01725 ,  G02F2001/0175 ,  G02F2001/01758 ,  G02F2203/69 ,  H01L31/125 ,  H01S5/0014 ,  H01S5/0085 ,  H01S5/02248 ,  H01S5/026 ,  H01S5/0262 ,  H01S5/0264 ,  H01S5/0265 ,  H01S5/0268 ,  H01S5/06256 ,  H01S5/06258 ,  H01S5/0683 ,  H01S5/06832 ,  H01S5/12 ,  H01S5/1228 ,  H01S5/2077 ,  H01S5/22 ,  H01S5/3408 ,  H01S5/4031 ,  H01S5/4087 ,  H01S5/50 ,  H04B10/2914 ,  H04B10/50 ,  H04J14/02 ,  H04J14/0246 ,  H04J14/025 ,  H04J14/0258 ,  H04J14/0265 ,  H04J14/0276 ,  H04J14/0282

Abstract: A method of in-wafer testing is provided for a monolithic photonic integrated circuit (PIC) formed in a semiconductor wafer where each such in-wafer circuit comprises two or more integrated electro-optic components, one of each in tandem forming a signal channel in the circuit. The method includes the provision of a first integrated photodetector at a rear end of each signal channel and a second integrated photodetector at forward end of each signal channel. Then, the testing is accomplished, first, by sequentially operating a first of a selected channel electro-optic component in a selected circuit to monitor light output from a channel via its first corresponding channel photodetector and adjusting its operating characteristics by detecting that channel electro-optic component output via its second corresponding channel photodetector to provide first calibration data. Second, by sequentially operating a second of a selected channel electro-optic component in the selected circuit to monitor signal output from the second selected channel electro-optic component via its second corresponding channel photodetector and adjusting its operating characteristics by detecting that channel electro-optic component output via its second corresponding channel photodetector to provide second calibration data. The first and second calibration data for each circuit channel for the selected circuit are then stored for future reference.

公开(公告)号：US07016571B2

公开(公告)日：2006-03-21

申请号：US11016241

申请日：2004-12-17

Applicant: Charles H. Joyner ,  Mark J. Missey ,  Radhakrishnan L. Nagarajan ,  Fred A. Kish, Jr.

Inventor： Charles H. Joyner ,  Mark J. Missey ,  Radhakrishnan L. Nagarajan ,  Fred A. Kish, Jr.

IPC: G02B6/34

CPC classification number: G02B6/12011 ,  G02B6/12016 ,  G02B6/12019 ,  G02B6/12023 ,  G02B6/132 ,  G02B6/42 ,  G02B2006/12097 ,  G02B2006/12176 ,  H01S5/026 ,  H01S5/0264 ,  H01S5/0265 ,  H01S5/0268 ,  H01S5/1014 ,  H01S5/2213 ,  H01S5/2231 ,  H01S5/227 ,  H01S5/4031 ,  H01S5/4087

Abstract: An arrayed waveguide grating (AWG) comprises at least two free space regions, a plurality of grating arms extending between the two space regions, a passivation layer formed over the arrayed waveguide grating and a plurality of inputs at least to one of the free space regions to receive a plurality of channel signals separated by a predetermined channel spacing. A depth of the passivation layer chosen by providing a TE to TM wavelength shift between TE and TM modes propagating through the arrayed waveguide grating being approximately less than or equal to 20% of a magnitude of the channel spacing.

Abstract translation: 阵列波导光栅（AWG）包括至少两个自由空间区域，在两个空间区域之间延伸的多个光栅臂，在阵列波导光栅上形成的钝化层，以及至少一个自由空间区域 以接收由预定信道间隔分开的多个信道信号。 通过在通过阵列波导光栅传播的TE和TM模式之间提供TE到TM波长移位而选择的钝化层的深度大约小于或等于信道间隔幅度的20％。

公开(公告)号：US06985648B2

公开(公告)日：2006-01-10

申请号：US10988067

申请日：2004-11-12

Applicant: Fred A. Kish, Jr. ,  Mark J. Missey ,  Radhakrishnan L. Nagarajan ,  Frank H. Peters ,  Richard P. Schneider ,  Charles H. Joyner

Inventor： Fred A. Kish, Jr. ,  Mark J. Missey ,  Radhakrishnan L. Nagarajan ,  Frank H. Peters ,  Richard P. Schneider ,  Charles H. Joyner

IPC: G02B6/12 ,  H04B10/08

CPC classification number: G02B6/12011 ,  B82Y20/00 ,  G01R31/31728 ,  G01R31/318511 ,  G02B6/12004 ,  G02B6/12007 ,  G02B6/12019 ,  G02B6/12021 ,  G02B6/12023 ,  G02B6/12026 ,  G02B6/12028 ,  G02B6/12033 ,  G02B6/131 ,  G02B6/136 ,  G02B6/4204 ,  G02F1/01725 ,  G02F2001/0175 ,  G02F2001/01758 ,  G02F2203/69 ,  H01L31/125 ,  H01S5/0014 ,  H01S5/0085 ,  H01S5/02248 ,  H01S5/026 ,  H01S5/0262 ,  H01S5/0264 ,  H01S5/0265 ,  H01S5/0268 ,  H01S5/06256 ,  H01S5/06258 ,  H01S5/0683 ,  H01S5/06832 ,  H01S5/12 ,  H01S5/1228 ,  H01S5/2077 ,  H01S5/22 ,  H01S5/3408 ,  H01S5/4031 ,  H01S5/4087 ,  H01S5/50 ,  H04B10/2914 ,  H04B10/50 ,  H04J14/02 ,  H04J14/0246 ,  H04J14/025 ,  H04J14/0258 ,  H04J14/0265 ,  H04J14/0276 ,  H04J14/0282

Abstract: A method of in-wafer testing is provided for a monolithic photonic integrated circuit (PIC) formed in a semiconductor wafer where each such in-wafer circuit comprises two or more integrated electro-optic components, one of each in tandem forming a signal channel in the circuit. The method includes the provision of a first integrated photodetector at a rear end of each signal channel and a second integrated photodetector at forward end of each signal channel. Then, the testing is accomplished, first, by sequentially operating a first of a selected channel electro-optic component in a selected circuit to monitor light output from a channel via its first corresponding channel photodetector and adjusting its operating characteristics by detecting that channel electro-optic component output via its second corresponding channel photodetector to provide first calibration data. Second, by sequentially operating a second of a selected channel electro-optic component in the selected circuit to monitor signal output from the second selected channel electro-optic component via its second corresponding channel photodetector and adjusting its operating characteristics by detecting that channel electro-optic component output via its second corresponding channel photodetector to provide second calibration data. The first and second calibration data for each circuit channel for the selected circuit are then stored for future reference.

Abstract translation: 提供了一种晶片内测试方法，用于形成在半导体晶片中的单片光子集成电路（PIC），其中每个这样的晶片内电路包括两个或更多个集成的电光部件，其中每一个串联形成信号通道 电路。 该方法包括在每个信号通道的后端提供第一集成光电检测器，并在每个信号通道的前端提供第二集成光电检测器。 然后，首先，通过顺序地操作所选择的电路中的所选择的通道电光部件中的第一个，以经由其第一对应的通道光电检测器监视从通道输出的光，并通过检测该通道电光元件来调整其工作特性， 通过其第二对应通道光电检测器输出光学部件以提供第一校准数据。 其次，通过在所选择的电路中顺序地操作所选择的通道电光部件中的第二个，以通过其第二对应的通道光电检测器监测从第二选定的通道电光部件输出的信号，并通过检测该通道电光 通过其第二对应通道光电检测器输出分量，以提供第二校准数据。 然后存储用于所选电路的每个电路通道的第一和第二校准数据以供将来参考。

公开(公告)号：US06891202B2

公开(公告)日：2005-05-10

申请号：US10319962

申请日：2002-12-16

Applicant: Fred A. Kish, Jr. ,  Sheila K. Mathis ,  Charles H. Joyner ,  Richard P. Schneider

Inventor： Fred A. Kish, Jr. ,  Sheila K. Mathis ,  Charles H. Joyner ,  Richard P. Schneider

IPC: H01L29/165 ,  H01L29/22 ,  H01L29/40 ,  H01L31/0304 ,  H01L31/109 ,  H01L31/153 ,  H01L33/14 ,  H01S5/00 ,  H01S5/026 ,  H01S5/20 ,  H01S5/22 ,  H01S5/223 ,  H01S5/227 ,  H01S5/343 ,  H01L33/00

CPC classification number: B82Y20/00 ,  H01L31/03046 ,  H01L31/109 ,  H01L33/145 ,  H01S5/026 ,  H01S5/2072 ,  H01S5/221 ,  H01S5/2224 ,  H01S5/2226 ,  H01S5/2227 ,  H01S5/2231 ,  H01S5/227 ,  H01S5/2275 ,  H01S5/3072 ,  H01S5/34306 ,  Y02E10/544

Abstract: An active semiconductor device, such as, buried heterostructure semiconductor lasers, LEDs, modulators, photodiodes, heterojunction bipolar transistors, field effect transistors or other active devices, comprise a plurality of semiconductor layers formed on a substrate with one of the layers being an active region. A current channel is formed through this active region defined by current blocking layers formed on adjacent sides of a designated active region channel where the blocking layers substantially confine the current through the channel. The blocking layers are characterized by being an aluminum-containing Group III-V compound, i.e., an Al-III-V layer, intentionally doped with oxygen from an oxide source. Also, wet oxide process or a deposited oxide source may be used to laterally form a native oxide of the Al-III-V layer. An example of a material system for this invention useful at optical telecommunication wavelengths is InGaAsP/InP where the Al-III-V layer comprises InAlAs:O or InAlAs:O:Fe. Other materials for the blocking layers may be InAlGaAs or alternating layers or alternating monolayers of AlAs/InAs. Thus, the O-doped blocking layers may be undoped, impurity doped or co-doped with Fe.

Abstract translation: 诸如掩埋异质结构半导体激光器，LED，调制器，光电二极管，异质结双极晶体管，场效应晶体管或其它有源器件的有源半导体器件包括形成在衬底上的多个半导体层，其中一层是有源区 。 通过由形成在指定的有源区通道的相邻侧上的电流阻挡层限定的有源区形成电流通道，其中阻挡层基本上限制电流通过通道。 阻挡层的特征在于含有铝的III-V族化合物，即有意从氧化物源掺杂氧的Al-III-V层。 此外，湿氧化物工艺或沉积的氧化物源可用于横向形成Al-III-V层的天然氧化物。 在光通信波长下用于本发明的材料系统的一个例子是InGaAsP / InP，其中Al-III-V层包括InAlAs：O或InAlAs：O：Fe。 用于阻挡层的其它材料可以是AlAlGaAs或AlAs / InAs的交替层或交替单层。 因此，O掺杂阻挡层可以是未掺杂的，杂质掺杂的或与Fe共掺杂的。

公开(公告)号：US06800500B2

公开(公告)日：2004-10-05

申请号：US10631001

申请日：2003-07-29

Applicant: Carrie Carter Coman ,  Fred A. Kish, Jr. ,  Michael R Krames ,  Paul S Martin

Inventor： Carrie Carter Coman ,  Fred A. Kish, Jr. ,  Michael R Krames ,  Paul S Martin

IPC: H01L2120

CPC classification number: H01L33/40 ,  H01L33/32 ,  H01S5/0216 ,  H01S5/0421 ,  H01S5/18341 ,  H01S5/32341

Abstract: A III-nitride light-emitting structure including a p-type layer, an n-type layer, and a light emitting layer is grown on a growth substrate. The III-nitride light-emitting structure is wafer bonded to a host substrate, then the growth substrate is removed. In some embodiments, a first electrical contact and first bonding layer are formed on the III-nitride light-emitting structure. A second bonding layer is formed on the host substrate. In such embodiments, wafer bonding the III-nitride light emitting structure to the host substrate comprises bonding the first bonding layer to the second bonding layer. After the growth substrate is removed, a second electrical contact may be formed on a side of the III-nitride light-emitting device exposed by removal of the growth substrate.

公开(公告)号：US06521914B2

公开(公告)日：2003-02-18

申请号：US10112175

申请日：2002-03-29

Applicant: Michael R Krames ,  Daniel A. Steigerwald ,  Fred A. Kish, Jr. ,  Pradeep Rajkomar ,  Jonathan J. Wierer, Jr. ,  Tun S Tan

Inventor： Michael R Krames ,  Daniel A. Steigerwald ,  Fred A. Kish, Jr. ,  Pradeep Rajkomar ,  Jonathan J. Wierer, Jr. ,  Tun S Tan

IPC: H01L29267

CPC classification number: H01L33/62 ,  G09G2360/148 ,  H01L25/167 ,  H01L27/156 ,  H01L33/20 ,  H01L33/38 ,  H01L33/405 ,  H01L33/641 ,  H01L33/647 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/14 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention is an inverted III-nitride light-emitting device (LED) with enhanced total light generating capability. A large area device has an n-electrode that interposes the p-electrode metallization to provide low series resistance. The p-electrode metallization is opaque, highly reflective, and provides excellent current spreading. The p-electrode at the peak emission wavelength of the LED active region absorbs less than 25% of incident light per pass. A submount may be used to provide electrical and thermal connection between the LED die and the package. The submount material may be Si to provide electronic functionality such as voltage-compliance limiting operation. The entire device, including the LED-submount interface, is designed for low thermal resistance to allow for high current density operation. Finally, the device may include a high-refractive-index (n>1.8) superstrate.

Abstract translation: 本发明是具有增强的总发光能力的反向III族氮化物发光器件（LED）。 大面积器件具有插入p电极金属化以提供低串联电阻的n电极。 p电极金属化是不透明的，高反射性的，并且提供优异的电流扩散。 LED有源区的峰值发射波长处的p电极每次吸收小于入射光的25％。 可以使用底座来提供LED管芯和封装之间的电连接和热连接。 底座材料可以是Si以提供诸如电压一致性限制操作的电子功能。 整个设备，包括LED-submount接口，设计用于低热阻，以实现高电流密度操作。 最后，器件可以包括高折射率（n> 1.8）的覆盖层。